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ICS853111AYL Datasheet(PDF) 8 Page - Integrated Device Technology |
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ICS853111AYL Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 19 page IDT™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER 8 ICS853111AY REV. C OCTOBER 25, 2007 ICS853111A LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER APPLICATION INFORMATION Figure 2A shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ V CC /2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio FIGURE 2A. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS LEVELS of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and V CC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. Single Ended Clock Input VCC PCLKx nPCLKx R1 C1 0.1u R2 1K 1K V_REF FIGURE 2B. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT Figure 2B shows an example of the differential input that can be wired to accept single ended LVPECL levels. The reference voltage level V BB generated from the device is connected to the negative input. The C1 capacitor should be located as close as possible to the input pin. WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS CLK_IN C1 0.1uF VDD(or VCC) + - VBB |
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