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TMS320C30 Datasheet(PDF) 9 Page - Texas Instruments |
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TMS320C30 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 54 page  TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 9 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 pin functions This section provides signal descriptions for the TMS320C30 in the microprocessor mode. The following tables list each signal, the number of pins, type of operating mode(s) (that is, input, output, or high-impedance state as indicated by I, O, or Z), and a brief description of its function. All pins labeled NC have special functions and should not be connected by the user. A line over a signal name (for example, RESET) indicates that the signal is active low (true at logic 0 level). The signals are grouped according to function. TMS320C30 Pin Functions PIN TYPE† DESCRIPTION CONDITIONS WHEN NAME QTY‡ TYPE† DESCRIPTION WHEN SIGNAL IS Z TYPE§ PRIMARY BUS INTERFACE D31 – D0 32 I/O/Z 32-bit data port of the primary bus interface S H R A23 – A0 24 O/Z 24-bit address port of the primary bus interface S H R R/W 1 O/Z Read / write for primary bus interface. R / W is high when a read is performed and low when a write is performed over the parallel interface. S H R STRB 1 O/Z External access strobe for the primary bus interface S H RDY 1 I Ready. RDY indicates that the external device is prepared for a primary-bus-interface transaction to complete. HOLD 1 I Hold for primary bus interface. When HOLD is a logic low, any ongoing transaction is completed. A23 – A0, D31 – D0, STRB, and R / W are in the high-impedance state and all transactions over the primary bus interface are held until HOLD becomes a logic high or the NOHOLD bit of the primary-bus-control register is set. HOLDA 1 O/Z Hold acknowledge for primary bus interface. HOLDA is generated in response to a logic low on HOLD. HOLDA indicates that A23 – A0, D31 – D0, STRB, and R / W are in the high-impedance state and that all transactions over the bus are held. HOLDA is high in response to a logic high of HOLD or when the NOHOLD bit of the primary-bus-control register is set. S EXPANSION BUS INTERFACE XD31 – XD0 32 I/O/Z 32-bit data port of the expansion bus interface S R XA12 – XA0 13 O/Z 13-bit address port of the expansion bus interface S R XR / W 1 O/Z Read / write signal for expansion bus interface. When a read is performed, XR / W is held high; when a write is performed, XR / W is low. S R MSTRB 1 O/Z External memory access strobe for the expansion bus interface S IOSTRB 1 O/Z External I / O access strobe for the expansion bus interface S XRDY 1 I Ready signal. XRDY indicates that the external device is prepared for an expansion- bus-interface transaction to complete. CONTROL SIGNALS RESET 1 I Reset. When RESET is a logic low, the device is in the reset condition. When RESET becomes a logic high, execution begins from the location specified by the reset vector. INT3 – INT0 4 I External interrupts IACK 1 O/Z Interrupt acknowledge. IACK is generated by the IACK instruction. IACK can be used to indicate the beginning or end of an interrupt-service routine. S MC / MP 1 I Microcomputer / microprocessor mode XF1, XF0 2 I/O/Z External flags. XF1 and XF0 are used as general-purpose I / Os or to support interlocked processor instructions. S R † I = input, O = output, Z = high-impedance state. All pins labeled NC have specified functions and should not be connected by the user. ‡ Quantity is the same for GEL and PPM packages unless otherwise noted. § S = SHZ active, H = HOLD active, R = RESET active |
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