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EVB71122

300 to 930MHz Receiver

Evaluation Board Description

39012 71122 01

Page 4 of 32

EVB Description

Rev. 001

Sept/06

1

Theory of Operation

1.1

General

The MLX71122 receiver architecture is based on a double-conversion super-heterodyne approach. The two

LO signals are derived from an on-chip integer-N PLL frequency synthesizer. The PLL reference frequency

is derived from a crystal (XTAL). The PLL synthesizer consists of an integrated voltage-controlled oscillator

with external inductor, a programmable feedback divider chain, a programmable reference divider, a phase-

frequency detector with a charge pump and an external loop filter.

In the receiver’s down-conversion chain, two mixers MIX1 and MIX2 are driven by the internal local oscillator

signals LO1 and LO2, respectively. The second mixer MIX2 is an image-reject mixer. As the first intermedi-

ate frequency (IF1) is very high (typically above 100 MHz), a reasonably high degree of image rejection is

provided even without using an RF front-end filter. At applications asking for very high image rejections,

cost-efficient RF front-end filtering can be realized by using a SAW filter in front of the LNA.

The receiver signal chain is setup by a low noise amplifier (LNA), two down-conversion mixers (MIX1 and

MIX2), an on-chip IF filter (IFF) as well as an IF amplifier (IFA). By choosing the required modulation via an

FSK/ASK switch (at pin MODSEL), either the on-chip FSK demodulator (FSK DEMOD) or the RSSI-based

ASK detector is selected. A second order data filter (OA1) and a data slicer (OA2) follow the demodulator.

The data slicer threshold can be generated from the mean-value of the data stream or by means of the posi-

tive and negative peak detectors (PKDET+/-).

In general the MLX71122 can be set to shut-down mode, where all receiver functions are completely turned

off, and to several other operating modes. There are two global operating modes that are selectable via the

logic level at pin SPISEL:

•

8-channel preconfigured mode (ABC mode)

•

fully programmable mode (SPI mode).

In ABC mode the number of frequency channels is limited to eight but no microcontroller programming is

required. In this case the three lines of the serial programming interface (SPI) are used to select one of the

eight predefined frequency channels via simple 3-bit parallel programming. Pins ENRX and MODSEL are

used to enable/disable the receiver and to select FSK or ASK demodulation, respectively.

SPI mode is recommended for full programming flexibility. In this case the three lines of the SPI are config-

ured as a standard 3-wire bus (SDEN, SDTA and SCLK). This allows changing many parameters of the

receiver, for example more operating modes, channels, frequency resolutions, gains, demodulation types,

data slicer settings and more. The pin MODSEL has no effect in this mode.

1.2

EVB Data Overview

! Input frequency ranges: 300 to 930MHz

! Power supply range: 3.0 to 5.5V

! Temperature range: -40 to +105°C

! Shutdown current: 50nA

! Operating current: 11mA (typ.)

! Internal IF2: 2MHz with 230kHz 3dB bandwidth

! Maximum data rate: 100kbps NRZ code,

50kbps bi-phase code

! Minimum frequency resolution: 10kHz

! Total image rejection: > 65dB (with external

RF front-end filter)

! FSK/FM deviation range: ±10 to ±50kHz

! Spurious emission: < -70dBm

! Linear RSSI range: > 70dB

! FSK input frequency acceptance range:

170kHz (3dB)

! Crystal reference frequency: 10MHz

! Input Sensitivity: at 4 kbps NRZ, BER = 3·10

-3

Frequency

315 MHZ

433 MHz

868 MHz

915 MHz

FSK: ±20 kHz deviation

-106dBm

-104dBm

-101dBm

-101dBm

ASK

-108dBm

-108dBm

-106dBm

-106dBm