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TH8055JDC Datasheet(PDF) 4 Page - Melexis Microelectronic Systems

Part # TH8055JDC
Description  Single Wire CAN Transceiver
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Manufacturer  MELEXIS [Melexis Microelectronic Systems]
Direct Link  http://www.melexis.com
Logo MELEXIS - Melexis Microelectronic Systems

TH8055JDC Datasheet(HTML) 4 Page - Melexis Microelectronic Systems

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TH8055
Single Wire CAN Transceiver
2. Functional Description
2.1
2.2
TxD Input Pin
TxD Polarity
TxD = logic 1 (or floating) on this pin produce an undriven or recessive bus state (low bus voltage)
TxD = logic 0 on this pin produce either a bus normal or a bus high voltage dominant state depending on the
transceiver mode state (high bus voltage)
If the TxD pin is driven to a logic low state while the sleep mode (Mode0=0 and Mode1=0) is activated, the
transceiver not drive the CANH pin to the dominant state.
The transceiver provides an internal pull up current on the TxD pin which will cause the transmitter to default
to the bus recessive state when TxD is not driven.
TxD input signals are standard CMOS logic levels.
Timeout Feature
In case of a faulty blocked dominant TxD input signal the CANH output is switched off automatically after the
specified TxD timeout reaction time to prevent a dominant bus.
The transmission is continued by next TxD L to H transition without delay.
Mode 0 and Mode 1 pins
The transceiver provides a weak internal pull down current on each of these pins which causes the
transceiver to default to sleep mode when they are not driven. The mode input signals are standard CMOS
logic level.
M0
M1
Mode
L
L
Sleep mode
H
L
High speed mode
L
H
Wake up
H
H
Normal mode
Sleep Mode
Transceiver is in low power state, waiting for wake up via high voltage signal or by mode pins change to any
state other than 0,0. In this state, the CANH pin is not in the dominant state regardless of the state of the
TxD pin.
High Speed Mode
This mode allows high speed download with bitrates up to 100Kbit/s. The output waveshaping circuit is
disabled in this mode. Bus transmitter drive circuits for those nodes which are required to communicate in
high speed mode are able to drive reduced bus resistance in this mode (see Table Static Characteristics).
High speed communications shall utilize the normal mode signal voltage levels as specified in Static
Characteristics.
TH8055 - Datasheet
Page 4 of 20
3901008055
May 2004
Rev 005


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