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EB1500DFN-BA Datasheet(PDF) 2 Page - Filtronic Compound Semiconductors |
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EB1500DFN-BA Datasheet(HTML) 2 Page - Filtronic Compound Semiconductors |
2 / 10 page Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Tel: +44 (0) 1325 301111 Fax: +44 (0) 1325 306177 Email: sales@filcs.com Website: www.filtronic.com 2 Datasheet v3.0 FPD1500DFN ABSOLUTE MAXIMUM RATING 1: Notes: PARAMETER SYMBOL TEST CONDITIONS ABSOLUTE MAXIMUM Drain-Source Voltage VDS -3V < VGS < +0V 8V Gate-Source Voltage VGS 0V < VDS < +8V -3V Drain-Source Current IDS For VDS > 2V IDss Gate Current IG Forward or reverse current 15mA RF Input Power 2 PIN Under any acceptable bias state 350mW Channel Operating Temperature TCH Under any acceptable bias state 175°C Storage Temperature TSTG Non-Operating Storage -55°C to 150°C Total Power Dissipation PTOT See De-Rating Note below 2.2W Gain Compression Comp. Under any bias conditions 5dB Simultaneous Combination of Limits 3 2 or more Max. Limits 1T Ambient = 22°C unless otherwise noted; exceeding any one of these absolute maximum ratings may cause permanent damage to the device 2Max. RF Input Limit must be further limited if input VSWR > 2.5:1 3Users should avoid exceeding 80% of 2 or more Limits simultaneously 4Total Power Dissipation defined as: P TOT ≡ (PDC + PIN) – POUT, where PDC: DC Bias Power, PIN: RF Input Power, POUT: RF Output Power Total Power Dissipation to be de-rated as follows above 22 °C: PTOT= 2.2 - (0.0167W/°C) x TPACK where TPACK= source tab lead temperature above 22°C (coefficient of de-rating formula is the Thermal Conductivity) Example: For a 65 °C carrier temperature: P TOT = 2.2W – (0.0167 x (65 – 22)) = 1.48W 5The use of a filled via-hole directly beneath the exposed heatsink tab on the bottom of the package is strongly recommended to provide for adequate thermal management. Ideally the bottom of the circuit board is affixed to a heatsink or thermal radiator BIASING GUIDELINES: • Active bias circuits provide good performance stabilization over variations of operating temperature, but require a larger number of components compared to self-bias or dual-biased. Such circuits should include provisions to ensure that Gate bias is applied before Drain bias, otherwise the pHEMT may be induced to self-oscillate • Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage supply for depletion-mode devices. • For standard Class A operation, a 50% of IDSS bias point is recommended. A small amount of RF gain expansion prior to the onset of compression is normal for this operating point. Note that pHEMTs, since they are “quasi- E/D mode” devices, exhibit Class AB traits when operated at 50% of IDSS. To achieve a larger separation between P1dB and IP3, an operating point in the 25% to 33% of IDSS range is suggested. Such Class AB operation will not degrade the IP3 performance. |
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