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ADUM2200ARWZ Datasheet(PDF) 8 Page - Analog Devices |
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ADUM2200ARWZ Datasheet(HTML) 8 Page - Analog Devices |
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8 / 20 page  ADuM2200/ADuM2201 Rev. 0 | Page 8 of 20 Parameter Symbol Min Typ Max Unit Test Conditions For All Models Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ VDD1 or VDD2 Logic High Input Threshold VIH 0.7 (VDD1 or VDD2) V Logic Low Input Threshold VIL 0.3 (VDD1 or VDD2) V Logic High Output Voltages VOAH, VOBH (VDD1 or VDD2) − 0.1 (VDD1 or VDD2) V IOx = −20 μA, VIx = VIxH (VDD1 or VDD2) − 0.5 (VDD1 or VDD2) − 0.2 V IOx = −4 mA, VIx = VIxH Logic Low Output Voltages VOAL, VOBL 0.0 0.1 V IOx = 20 μA, VIx = VIxL 0.04 0.1 V IOx = 400 μA, VIx = VIxL 0.2 0.4 V IOx = 4 mA, VIx = VIxL SWITCHING SPECIFICATIONS ADuM220xAR Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 tPHL, tPLH 15 150 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels Propagation Delay Skew6 tPSK 50 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching7 tPSKCD/OD 50 ns CL = 15 pF, CMOS signal levels Output Rise/Fall Time (10% to 90%) tR/tF 10 ns CL = 15 pF, CMOS signal levels ADuM220xBR Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 tPHL, tPLH 15 55 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|5 PWD 3 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 tPSK 22 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Codirectional Channels7 tPSKCD 3 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Opposing Directional Channels7 tPSKOD 22 ns CL = 15 pF, CMOS signal levels Output Rise/Fall Time (10% to 90%) tR/tF 5 V/3 V Operation 3.0 ns CL = 15 pF, CMOS signal levels 3 V/5 V Operation 2.5 ns CL = 15 pF, CMOS signal levels 5 V/3 V Operation 3.0 ns CL = 15 pF, CMOS signal levels 3 V/5 V Operation 2.5 ns CL = 15 pF, CMOS signal levels For All Models Common-Mode Transient Immunity at Logic High Output8 |CMH| 25 35 kV/μs VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V Common-Mode Transient Immunity at Logic Low Output8 |CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V Refresh Rate fr 5 V/3 V Operation 1.2 Mbps 3 V/5 V Operation 1.1 Mbps Input Dynamic Supply Current, per Channel9 IDDI (D) 5 V/3 V Operation 0.19 mA/Mbps 3 V/5 V Operation 0.10 mA/Mbps |
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