CY2SSTU877

Rev 1.0, November 21, 2006

Page 4 of 8

Notes:

1. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters (used for

low speed system debug).

2. Application clock frequency indicates a range over which the PLL must meet all timing requirements.

AC Timing Specifications

Parameter

Description

Conditions

Min.

Max.

Unit

[1,2]

Clock Frequency (Max)

125

500

MHz

Clock Frequency (Application)

250

500

MHz

Input Duty Cycle

40

60

%

Output Duty Cycle

48

52

%

PLL Lock Time

–

15

s

Output Enable Time

OE to any CLKT/ CLKC[0:9]

–

8

ns

Output Disable Time

OE to any CLKT/ CLKC[0:9]

–

8

ns

Tjitt (cc)

Cycle-to-cycle jitter

–40

40

ps

Tjit (Period)

Period jitter

–30

30

ps

Tjit (H-Period)

Half Period Cycle-to-cycle jitter

Above 270 MHz

–45

45

ps

Below 270 MHz

–60

60

ps

Static Phase Offset

Average 1000 cycles

–50

50

ps

Dynamic Phase Offset

–40

40

ps

Clock Skew

–

40

ps

Output Slew Rate

CLKT/ CLKC[0:9], FB_OUTT,

FB_OUTC

1.5

4

V/ns

Input Slew Rate

CLK_INT, CLK_INC, FB_INT,

FB_INC

14

V/ns

OE

0.5

V/ns

Figure 1. Test Loads for Timing Measurement