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CY28RS480OXC Datasheet(PDF) 5 Page - SpectraLinear Inc |
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CY28RS480OXC Datasheet(HTML) 5 Page - SpectraLinear Inc |
5 / 14 page CY28RS480 Rev 1.0, November 22, 2006 Page 5 of 14 Byte 2: Control Register 2 Bit @Pup Name Description 7 1 CPUT/C SRCT/C Spread Spectrum Selection ‘0’ = –0.35% ‘1’ = –0.50% 6 1 USB_48 48-MHz Output Drive Strength 0 = 2x, 1 = 1x 5 1 PCI 33-MHz Output Drive Strength 0 = 2x, 1 = 1x 4 0 Reserved Reserved 3 1 Reserved Reserved 20 CPU SRC CPU/SRC Spread Spectrum Enable 0 = Spread off, 1 = Spread on 1 1 Reserved Reserved 0 1 Reserved Reserved Byte 3: Control Register 3 Bit @Pup Name Description 7 1 CLKREQ# CLKREQ# drive mode 0 = SRC clocks driven when stopped, 1 = SRC clocks tri-state when stopped 6 0 CPU CPU pd drive mode 0 = CPU clocks driven when power-down, 1 = CPU clocks tri-state 5 1 SRC SRC pd drive mode 0 = SRC clocks driven when power-down, 1 = SRC clocks tri-state 4 0 Reserved Reserved 3 1 Reserved Reserved 2 1 Reserved Reserved 1 1 Reserved Reserved 0 1 HTT66 HTT66 Output Drive Strength0 = High drive, 1 = Low drive. Byte 4: Control Register 4 Bit @Pup Name Description 7 0 SRC[T/C]5 SRC[T/C]5 CLKREQ0 control 1 = SRC[T/C]5 stoppable by CLKREQ#0 pin 0 = SRC[T/C]5 free running 6 0 SRC[T/C]4 SRC[T/C]4 CLKREQ#0 control 1 = SRC[T/C]4 stoppable by CLKREQ#0 pin 0 = SRC[T/C]4 free running 5 0 SRC[T/C]3 SRC[T/C]3 CLKREQ#0 control 1 = SRC[T/C]3 stoppable by CLKREQ#0 pin 0 = SRC[T/C]3 free running 4 0 SRC[T/C]2 SRC[T/C]2 CLKREQ#0 control 1 = SRC[T/C]2 stoppable by CLKREQ#0 pin 0 = SRC[T/C]2 free running 3 0 SRC[T/C]1 SRC[T/C]1 CLKREQ#0 control 1 = SRC[T/C]1 stoppable by CLKREQ#0 pin 0 = SRC[T/C]1 free running 2 0 SRC[T/C]0 SRC[T/C]0 CLKREQ#0 control 1 = SRC[T/C]1 stoppable by CLKREQ#0 pin 0 = SRC[T/C]1 free running 1 1 HTT66 HTT66 Output enable 0 = Disabled, 1 = Enabled |
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