CY28RS480

Rev 1.0, November 22, 2006

Page 8 of 14

CLK_REQ[0:1]# Description

The CLKREQ#[1:0] signals are active low input used for clean

stopping and starting selected SRC outputs. The outputs

controlled by CLKREQ#[1:0] are determined by the settings in

register bytes 4 and 5. The CLKREQ# signal is a debounced

signal in that its state must remain unchanged during two

consecutive rising edges of DIFC to be recognized as a valid

assertion or deassertion. (The assertion and deassertion of

this signal is absolutely asynchronous.)

CLK_REQ[0:1]# Deassertion [Low to High Transition]

The impact of deasserting the CLKREQ#[1:0] pins is all DIF

outputs that are set in the control registers to stoppable via

assertion of CLKREQ#[1:0] are to be stopped after their next

transition. When the control register CLKREQ# drive mode bit

is programmed to ‘0’, the final state of all stopped SRC signals

is SRCT clock = High and SRCC = Low. There is to be no

change to the output drive current values, SRCT will be driven

high with a current value equal 6 x Iref,. When the control

register CLKREQ# drive mode bit is programmed to ‘1’, the

final state of all stopped DIF signals is low, both SRCT clock

and SRCC clock outputs will not be driven.

CLK_REQ[0:1]# Assertion [High to Low Transition]

All differential outputs that were stopped are to resume normal

operation in a glitch free manner. The maximum latency from

the Assertion to active outputs is between 2–6 SRC clock

periods (2 clocks are shown) with all SRC outputs resuming

simultaneously.

If

the

CLKREQ#

drive

mode

bit

is

programmed to ‘1’ three-state), the all stopped SRC outputs

must be driven high within 10 ns of CLKREQ#[1:0] Assertion

to a voltage greater than 200 mV.

Figure 3. CLK_REQ#[0:1] Assertion/Deassertion Waveform

SRCT(stoppable)

SRCT(stoppable)

SRCC(free running)

SRCT(free running)

CLKREQ#X