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RF2460
Rev B6 DS080128
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
Pin
Function
Description
Interface Schematic
1ENABLE
Power down pin. A logic “low” turns the part off. A logic “high” (>1.6V)
turns the part on.
2VCC1
Supply Voltage for the LNA, mixer, bias, and logic circuitry. External RF and
IF bypassing is required. The trace length between the pin and the bypass
capacitors should be minimized. The ground side of the bypass capacitors
should connect immediately to ground plane.
See pin 20.
3VCC2
Supply Voltage for the LO buffer amplifier. External RF and IF bypassing is
required. The trace length between the pin and the bypass capacitors
should be minimized. The ground side of the bypass capacitors should con-
nect immediately to ground plane.
4LO IN
Mixer LO Input Pin.
5NC
No connection. For isolation purposes, this pin is connected to the ground
plane.
6NC
No connection. For isolation purposes, this pin is connected to the ground
plane.
7IF+
CDMA IF Output pin. This is a balanced output. The internal circuitry, in
conjunction with an external matching/bias inductor to V
CC, sets the oper-
ating impedance. This inductor is typically incorporated in the matching
network between the output and IF filter. The part is designed to drive a
1k
Ω load. Because this pin is biased to V
CC, a DC blocking capacitor must
be used if the IF filter input has a DC path to ground. See Application Sche-
matic.
8NC
No connection. For isolation purposes, this pin is connected to the ground
plane.
9IF-
Same as pin 7, except complementary output.
See pin 6.
10
NC
No connection. For isolation purposes, this pin is connected to the ground
plane.
11
LNA2 E
Emitter for LNA2. Increasing the inductance on this pin will reduce the
mixer gain, increase IP3 and noise figure.
12
MIX IN
Mixer RF Input Pin. This pin is internally DC biased and should be DC
blocked if connected to a device with DC present. External matching net-
work sets RF and IF impedance for optimum performance.
13
ISET2
This pin is used to set the bias current and IIP3 of the mixer amplifier using
a resistor to ground. See plots for values and current settings.
14
ISET1
This pin is used to set the bias current and IIP3 of the LNA amplifier using a
resistor to ground. See plots for values and current settings.
15
LNA OUT
LNA output pin. Open collector.
See pin 20.
16
MIX GAIN
CMOS compatible signal controlling mixer gain mode. Setting this signal
high places the mixer in the high gain mode. Setting this signal low places
the mixer in low gain mode by bypassing and shutting off the mixer buffer
amplifier current.
17
LNA GAIN
CMOS compatible signal controlling LNA gain mode. Setting this signal high
places the LNA in the high gain mode. Setting this signal low bypasses the
LNA and shuts off the LNA bias current.
18
NC
No connection. For isolation purposes, this pin is connected to the ground
plane.
19
NC
No connection. For isolation purposes, this pin is connected to the ground
plane.
IF1-
IF1+
1.2 pF
1.2 pF
GND2
MIX IN
MIX GAIN
LNA GAIN