PRELIMINARY

Spread Spectrum Timing Solution for Serverworks Chipset

CY28158

Rev 1.0, November 20, 2006

Page 1 of 9

2200 Laurelwood Road, Santa Clara, CA 95054

Tel:(408) 855-0555

Fax:(408) 855-0550

www.SpectraLinear.com

Features

• Maximized EMI suppression using Cypress’s spread

spectrum technology

• Based on Industry Standard CK133 Pinout with all

outputs compliant to CK98 specifications

• 0.5% downspread outputs deliver up to 10dB lower EMI

• 6 skew-controlled copies of CPU output

• 6 copies of PCI output (synchronous w/CPU output)

• 2 copies of 66 MHz fixed frequency 3.3V clock

• 3 copies of 16.67 MHz IOAPIC clock, synchronous to

CPU clock

• 1 copy of 48 MHz USB output

• 2 copies of 14.31818 MHz reference clock

• Programmable to 133 or 100 MHz operation

• Power management control pins for clock stop and

shut down

• Available in 56-pin SSOP

Key Specifications

CPU Output Jitter: ................................................... .<150 ps

CPU Output Skew:.................................................... <175 ps

CPU to 3V66 Output Offset:

0.0 to1.5 ns

(CPU leads)

CPU to IOAPIC Output Offset

1.5 to 4.0 ns (CPU leads)

CPU to PCI Output Offset ................. 0 to 4.0 ns (CPU leads)

Table 1. Pin Selectable Frequency

SEL133/100#

CPU0:5 (MHz)

PCI

1

133

33.3

0

100

33.3

Block Diagram

Pin Configuration

GND_REF

REF0

REF1

VDD_REF

X1

X2

GND_PCI

GND_PCI

PCI_F

VDD_PCI

PCI1

PCI2

GND_PCI

PCI3

PCI4

VDD_PCI

VDD_PCI

PCI5

GND_PCI

GND_3V66

GND_3V66

VDD_3V66

VDD_3V66

GND_3V66

VDD_IOAPIC

IOAPIC2

IOAPIC1

IOAPIC0

GND_IOAPIC

VDD_CPU

CPU5

CPU4

GND_CPU

VDD_CPU

CPU3

CPU2

GND_CPU

VDD_CPU

CPU1

CPU0

GND_CPU

VDDA

GNDA

PCI_STOP#

CPU_STOP#

PWR_DWN#

SPREAD#

SEL1

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

32

31

30

29

3V66_0

3V66_1

VDD_3V66

SEL133/100#

SEL0

VDD_48MHZ

48MHZ

GND_48MHZ

REF0:1

CPU0:5

3V66_0:1

XTAL

PLL 1

SPREAD#

X2

X1

PCI_F

PCI1:5

IOAPIC0:2

PLL2

OSC

STOP

Logic

Power

Tristate

Logic

SEL0

SEL1

SEL133/100#

Clock

CPU_STOP#

÷2/÷1.5

STOP

Logic

Clock

Down

Logic

÷2

STOP

Logic

Clock

÷2

2

6

2

1

5

3

1

PCI_STOP#

PWRDWN#

48MHz