ADC12081_02 datasheet(6/17 Pages) NSC | 12-Bit, 5MHz Self-Calibrating, Pipelined A/D Converter with Internal Samble & Hold

6 page

DC and Logic Electrical Characteristics

The following specifications apply for AGND = DGND = DGND I/O = 0V, V

A =VD =VD I/O = +5V, PD = +5V, VREF = +2.0V,

CLK = 50MHz, CL = 50 pF/pin. After Auto-Cal at Temperature. Boldface limits apply for TA =TMIN to TMAX; all other limits

A =TJ = 25˚C (Note 7) (Note 8) and (Note 9)

Symbol

Parameter

Conditions

Typical

Limits

Units

(Limits)

CLK, OE Digital Input Characteristics

Logical "1" Input Voltage

V+ = 5.25V

2.0

V(min)

Logical "0" Input Voltage

V+ = 4.75V

0.8

V(min)

Logical "1" Input Current

IN = 5.0V

µA

Logical "0" Input Current

IN =0V

−5

µA

IN Input Capacitance

D0 - D11 Digital Output Characteristics

Logical "1" Output Voltage

OUT = −1mA

V (min)

Logical "0" Output Voltage

OUT = 1.6mA

0.4

V (max)

TRI-STATE®Output Current

OUT = 3Vor5V

µA

OUT = 0V

−10

µA

Output Short Circuit Source

Current

VDDO= 3V, V

OUT = 0V

−14

mA(min)

−I

Output Short Circuit Sink Current

VDDO= 3V, V

OUT =VO

mA(min)

Power Supply Characteristics

Analog Supply Current

PD = VDDO

PD = DGND

2.5

mA(max)

Digital Supply Current

PD = VDDO

PD = DGND

0.5

mA(max)

Total Power Consumption

PD = VDDO

PD = DGND

105

140

mW(max)

AC Electrical Characteristics

The following specifications apply for AGND = DGND = DGND I/O = 0V, V

A =VD =VD I/O = +5V, PD = +5V, VREF = +2.0V,

CLK = 5 MHz, CL = 50 pF/pin. After Auto-Cal at Temperature. Boldface limits apply for TA =TMIN to TMAX; all other limits TA

J = 25˚C (Note 7) (Note 8) and (Note 10)

Symbol

Parameter

Conditions

Typical

Limits

Units

(Limits)

CLK

Clock Frequency

0.5

MHz(min)

MHz(max)

Clock Duty Cycle

CONV

Conversion Latency

10.25

Clock

Cycles

Aperture Delay Time

3.5

Data output delay after rising clk

edge

D I/O=3V

D I/O=5V

DIS

Data outputs into Tristate mode

nA (max)

Data outputs active after Tristate

ns (max)

WCAL

Calibration request pulse width

Tclk(min)

RDYC

Ready Low after CAL request

Tclk

CAL

Calibration cycle

4000

Tclk

WPD

Power-down pulse width

Tclk(min)

RDYPD

Ready Low after PD request

Tclk

Power down mode exit cycle

4000

Tclk

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