CY28324 datasheet(6/21 Pages) SPECTRALINEAR | FTG for Intel® Pentium® 4 CPU and Chipsets

6 page

CY28324

Rev 1.0, November 20, 2006

Page 6 of 21

Data Byte Configuration Map

Table 3. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Bit

Description

Bit

Description

1Start

2:8

Slave address – 7 bits

2:8

Slave address – 7 bits

9Write

Acknowledge from slave

11:18

Command Code – 8 bits

‘1xxxxxxx’ stands for byte operation

bit[6:0] of the command code represents the offset

of the byte to be accessed

11:18

Command Code – 8 bits

‘1xxxxxxx’ stands for byte operation

bit[6:0] of the command code represents the offset

of the byte to be accessed

Acknowledge from slave

20:27

Data byte – 8 bits

Repeat start

Acknowledge from slave

21:27

Slave address – 7 bits

Stop

Read

Acknowledge from slave

30:37

Data byte from slave – 8 bits

Not acknowledge

Stop

Data Byte 0

Bit

Pin#

Name

Description

Power-On

Default

Bit 7

Spread Select2

‘000’ = OFF

‘001’ = Reserved

‘010’ = Reserved

‘011’ = Reserved

‘100’ = ± 0.25%

‘101’ = – 0.5%

‘110’ = ±0.5%

‘111’ = ±0.38%

Bit 6

Spread Select1

Bit 5

Spread Select0

Bit 4

SEL4

SW Frequency selection bits. See

Table 4.0

Bit 3

SEL3

Bit 2

SEL2

Bit 1

SEL1

Bit 0

SEL0

Data Byte 1

Bit

Pin#

Name

Description

Power-On

Default

Bit 7

38, 37

CPU1, CPU1#

(Active/Inactive)

Bit 6

41, 40

CPU0, CPU0#

(Active/Inactive)

Bit 5

48MHz

(Active/Inactive)

Bit 4

24_48MHz

(Active/Inactive)

Bit 3

3V66_3

(Active/Inactive)

Bit 2

3V66_2

(Active/Inactive)

Bit 1

3V66_1

(Active/Inactive)

Bit 0

3V66_0

(Active/Inactive)

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