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CY28326OXCT Datasheet(PDF) 5 Page - SpectraLinear Inc |
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CY28326OXCT Datasheet(HTML) 5 Page - SpectraLinear Inc |
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5 / 22 page  CY28326 Rev 1.0, November 20, 2006 Page 5 of 22 Byte Configuration Map 46 Acknowledge from slave 38 Acknowledge .... Data Byte /Slave Acknowledges 46:39 Data byte 1 from slave – 8 bits .... Data Byte N –8 bits 47 Acknowledge .... Acknowledge from slave 55:48 Data byte 2 from slave – 8 bits .... Stop 56 Acknowledge .... Data bytes from slave / Acknowledge .... Data Byte N from slave – 8 bits .... NOT Acknowledge ... Stop Table 5. Block Read and Block Write protocol (continued) Table 6. Byte Read and Byte Write protocol Byte Write Protocol Byte Read Protocol Bit Description Bit Description 1Start 1Start 8:2 Slave address – 7 bits 8:2 Slave address – 7 bits 9Write 9Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code – 8 bits 18:11 Command Code – 8 bits 19 Acknowledge from slave 19 Acknowledge from slave 27:20 Data byte – 8 bits 20 Repeated start 28 Acknowledge from slave 27:21 Slave address – 7 bits 29 Stop 28 Read 29 Acknowledge from slave 37:30 Data from slave – 8 bits 38 NOT Acknowledge 39 Stop Byte 0: Control Register Bit @Pup Name/Pin Affected Description 7 HW FSD HW Frequency selection bits [3:0]. See table 2. Power up latched value 6HW FSC 5HW FSB 4HW FSA 3 0 Test bit Don’t change, Default =0 2 1 CPU[T/C]2 CPU[T/C]2 Output Enable 0 = Disabled (tri-sate), 1 = Enabled 1 1 CPU[T/C]1 CPU[T/C]1 Output Enable 0 = Disabled (tri-sate), 1 = Enabled 0 1 CPU[T/C]0 CPU[T/C]0 Output Enable 0 = Disabled (tri-sate), 1 = Enabled |
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