CY28341OC-3 datasheet(11/19 Pages) SPECTRALINEAR

Part #	CY28341OC-3

Description	Universal Clock Chip for VIA?줡4M/KT/KM400A DDR Systems

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Manufacturer	SPECTRALINEAR [SpectraLinear Inc]

Direct Link	http://www.spectralinear.com

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11 / 19 page

CY28341-3

Rev 1.0, November 21, 2006

Page 11 of 19

Power-down Deassertion (K7 Mode)

When deasserted PD# to high level, all clocks are enabled and

start running on the rising edge of the next full period in order

to guarantee a glitch free operation, no partial clock pulses.

PCI 33MHz

PD#

REF 14.318MHz

USB 48MHz

DDRT 133MHz

DDRC 133MHz

AGP 66MHz

CPUOD_C 133MHz

CPUCS_C 133MHz

CPUOD_T 133MHz

CPUCS_T 133MHz

Figure 4. Power-down Assertion Timing Waveform (In K7 Mode)

PC I 3 3 M H z

PD #

CP UT 1 3 3 M H z

CP UC 1 3 3 M H z

AG P 6 6 M H z

R E F 14.318 M H z

U SB 4 8 M H z

< 1 .5 m sec

DDRT 1 3 3 M H z

DDRC 1 3 3 M Hz

Figure 5. Power-down Deassertion Timing Waveform (in K7 Mode)

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