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CY28341OXC-2T Datasheet(PDF) 11 Page - SpectraLinear Inc |
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CY28341OXC-2T Datasheet(HTML) 11 Page - SpectraLinear Inc |
11 / 18 page CY28341-2 Rev 1.0, November 21, 2006 Page 11 of 18 AMD K7 processor SELP4_K7# = 0 Power-down Assertion (K7 Mode) When the PD# signal is asserted LOW, all clocks are disabled to a low level in an orderly fashion prior to removing power from the part. When PD# is asserted (forced) LOW, the device transitions to a shutdown (power-down) mode and all power supplies may then be removed. When PD# is sampled LOW by two consecutive rising edges of CPU clock, then all affected clocks are stopped in a LOW state as soon as possible. When in power-down (and before power is removed), all outputs are synchronously stopped in a LOW state (see Figure 3 below), all PLL’s are shut off, and the crystal oscillator is disabled. When the device is shut down, the I2C function is also disabled. P C I 33M H z P W RDW N# CP U 1 3 3 M Hz CP U# 1 3 3 M Hz A G P 66M H z R E F 14.318M H z US B 4 8 M Hz < 1 .5 m s e c S D R A M 133M H z DDRT 133M H z DDRC 133M H z Figure 3. Power-down Deassertion Timing Waveform (in P4 mode) PC I 33M H z PW R D W N # R E F 14.318M H z USB 48M H z S D R A M 133M H z DD RT 133M Hz DD RC 133M Hz AG P 66M H z C P U O D _C 133M H z CPU CS_C 133M Hz C P UOD_T 133M Hz C P U C S _T 133M H z Figure 4. Power-down Assertion Timing Waveform (in K7 mode) |
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