CY28346

Rev 1.0, November 24, 2006

Page 3 of 19

Two-Wire SMBus Control Interface

The two-wire control interface implements a Read/Write slave

only interface according to SMBus specification.

The device will accept data written to the D2 address and data

may read back from address D3. It will not respond to any

other addresses, and previously set control registers are

retained as long as power in maintained on the device.

Serial Control Registers

Following the acknowledge of the Address Byte, two additional

bytes must be sent:

1. “Command code” byte

2. “Byte count” byte.

Although the data (bits) in the command is considered “don’t

care,” it must be sent and will be acknowledged. After the

Command Code and the Byte Count have been acknowl-

edged, the sequence (Byte 0, Byte 1, and Byte 2) described

below will be valid and acknowledged.

Bit

@Pup

Pin#

Description

7

0

Spread Spectrum Enable. 0 = Spread Off, 1 = Spread On

This is a Read and Write control bit.

6

0

CPU Clock Power-down Mode Select. 0 = Drive CPUT(0:2) to 4 or 6 IREF and drive

CPUC(0:2) LOW when PD# is asserted LOW. 1 = Tri-state all CPU outputs. This is only

applicable when PD# is LOW. It is not applicable to CPU_STP#.

5

0

35

3V66_1/VCH Frequency Select, 0 = 66M selected, 1 = 48M selected

This is a Read and Write control bit.

4

Pin 53

44,45,48,49,5

1,52

CPU_STP#. Reflects the current value of the external CPU_STP# (pin 53) This bit is

Read-only.

3

Pin 34

10,11,12,13,16

,17,18

Reflects the current value of the internal PCI_STP# function when read. Internally PCI_STP#

is a logical AND function of the internal SMBus register bit and the external PCI_STP# pin.

2

Pin 40

Frequency Select Bit 2. Reflects the value of SEL2 (pin 40). This bit is Read-only.

1

Pin 55

Frequency Select Bit 1. Reflects the value of SEL1 (pin 55). This bit is Read-only.

0

Pin 54

Frequency Select Bit 0. Reflects the value of SEL0 (pin 54). This bit is Read-only.

Byte 1: CPU Clock Register

Bit

@Pup

Pin#

Description

7

Pin 43

43

MULT0 (Pin 43) Value. This bit is Read-only.

6

0

53

CPUT/C(0:2) Output Functionality Control When CPU_STP# is Asserted. 0 = Drive

CPUT(0:2) to 4 or 6 IREF and drive CPUC(0:2) LOW when CPU_STP# asserted LOW.

1 = three-state all CPU outputs. This bit will override Byte0,Bit6 such that even if it is 0,

when PD# goes LOW the CPU outputs will be three-stated.

5

0

44,45

CPU2 Functionality Control When CPU_STP# is Asserted LOW. 1 = Free Running, 0 =

Stopped LOW with CPU_STP# asserted LOW. This is a Read and Write control bit.

4

0

48,49

CPU1 Functionality Control When CPU_STP# is Asserted LOW. 1 = Free Running, 0 =

Stopped LOW with CPU_STP# asserted LOW. This is a Read and Write control bit.

3

0

51,52

CPUT0 Functionality Control When CPU_STP# is Asserted LOW. 1 = Free Running, 0 =

Stopped LOW with CPU_STP# asserted LOW. This is a Read and Write control bit.

2

1

44,45

CPUT/C2 Output Control. 1 = enabled, 0 = disable HIGH and CPUC2 disables LOW. This

is a Read and Write control bit.

1

1

48,49

CPUT/C1 Output Control. 1 = enabled, 0 = disable HIGH and CPUC1 disables LOW. This

is a Read and Write control bit.

0

1

51,52

CPUT/C0 Output Control. 1 = enabled, 0 = disable HIGH and CPUC0 disables LOW. This

is a Read and Write control bit.

Notes:

2. PU = internal pull-up. PD = internal pull-down. T = tri-level logic input with valid logic voltages of LOW = < 0.8V, T = 1.0 – 1.8V and HIGH = > 2.0V.

3. The “Pin#” column lists the relevant pin number where applicable. The “@Pup” column gives the default state at power-up.