CY28347

Rev 1.0, November 20, 2006

Page 10 of 21

P4 Mode CPU at 0.7V

TDC

CPUT/C Duty Cycle

45554555

45

55

45

55

% 5,6,10,14,15

TPeriod

CPUT/C Period

14.85

15.3

9.85

10.2

7.35

7.65

4.85

5.1

ns 5,6,10,14,15

Tr/Tf

CPUT/C Rise and Fall

Times

175

700

175

700

175

700

175

700

ps 15,16

Rise/Fall Matching

20%

20%

20%

20%

16,17

Delta Tr/Tf Rise/Fall Time Variation

125

125

125

125

ps 10,15,16,18

TSKEW

CPUT/C to CPUCS_T/C

Clock Skew

100

100

100

100

ps 10,11,12,14,1

5

TCCJ

CPUT/C Cycle-to-Cycle

Jitter

150

150

150

150

ps 6,10,11,12,14,

15

Vcross

Crossing Point Voltage

280

430

280

430

280

430

280

430

mV 15.

P4 Mode CPU at 1.0V

TDC

CPUT/C Duty Cycle

45554555

45

55

45

55

% 5,10,6,14

TPeriod

CPUT/C Period

14.85

15.3

9.85

10.2

7.35

7.65

4.85

5.1

nS 5,10,6,14

Differ-

ential Tr/Tf

CPUT/C Rise and Fall

Times

175

467

175

467

175

467

175

467

ps 10,11,19

Delta Tr/Tf Rise/Fall Time Variation

125

125

125

125

ps 10,18

TSKEW

CPUT/C to CPUCS_T/C

Clock Skew

100

100

100

100

ps 10,11,12,14

TCCJ

CPUT/C Cycle-to-Cycle

Jitter

150

150

150

150

ps 10,11,12,14

Vcross

Crossing Point Voltage

510

760

510

760

510

760

510

760

mV 19

SE-

DeltaSlew

Absolute Single-ended

Rise/Fall Waveform

Symmetry

325

325

325

325

ps 20

K7 Mode

TDC

CPUOD_T/C Duty Cycle

45554555

45

55

45

55

% 5,6,10

TPeriod

CPUOD_T/C Period

14.85

15.3

9.85

10.2

7.35

7.65

4.85

5.1

ns 5,6,10

TLOW

CPUOD_T/C LOW Time

2.8

2.8

1.67

2.8

ns 5,6,10

Tf

CPUOD_T/C Fall Time

0.4

1.6

0.4

1.6

0.4

1.6

0.4

1.6

ns 5,10,21

TCCJ

CPUOD_T/C

Cycle-to-Cycle Jitter

±250

±250

±250

±250

ps 6,10

VD

Differential Voltage AC

.4

Vp+.6V

.4

Vp+.6V

.4

Vp+.6V

.4

Vp+.6V

V 22

VX

Differential Crossover

Voltage

500

1100

500

1100

500

1100

500

1100

mV 23

Chipset

TDC

CPUCS_T/C Duty Cycle

45

55

45

55

45

55

45

55

% 5,10,6

Notes:

14. Measured at VX between the rising edge and the following falling edge of the signal.

15. Determined as a fraction of 2*(Trise-Tfall)/(Trise+Tfall).

16. See figure 6 for 0.7V loading specification.

17. Measurement taken from differential waveform, from -0.35V to +0.35V.

18. The time specified is measured from when all VDD’s reach their respective supply rail (3.3V and 2.5V) till the frequency output is stable and operating within

specifications.

19. Ideally the probes should be placed on the pins. If there is a transmission line between the test point and the pin for one signal of the pair (e.g., CPU), you should

add the same length transmission line to the other signal of the pair (e.g., AGP).

20. Measured in absolute voltage, i.e., single-ended measurement.

21. Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals and at 1.25V for 2.5V, and 50% point for differential signals.

22. Measured at VX, or where subtraction of CLK–CLK# crosses 0 volts.

23. VD is the magnitude of the difference between the measured voltage level on a DDRT (and CPUCS_T) clock and the measured voltage level on its complementary

DDRC (and CPUCS_C) one.

Parameter

Description

66 MHz

100 MHz

133 MHz

200 MHz

Unit

Notes

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.