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CY28359OCT Datasheet(PDF) 2 Page - SpectraLinear Inc

Part # CY28359OCT
Description  273 MHz 6 Output Buffer for DDR400 DIMMS
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Manufacturer  SPECTRALINEAR [SpectraLinear Inc]
Direct Link  http://www.spectralinear.com
Logo SPECTRALINEAR - SpectraLinear Inc

CY28359OCT Datasheet(HTML) 2 Page - SpectraLinear Inc

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CY28359
Rev 1.0, November 24, 2006
Page 2 of 7
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. The interface can also be
accessed during power down operation.
Data Protocol
The clock driver serial protocol accepts Byte Write, Byte Read,
Block Write and Block Read operation from any external I2C
controller. For Block Write/Read operation, the bytes must be
accessed in sequential order from lowest to highest byte (most
significant bit first) with the ability to stop after any complete
byte has been transferred. For Byte Write and Byte Read
operations, the system controller can access individual
indexed bytes. The offset of the indexed byte is encoded in the
command code, as described in Table 1.
The Block Write and Block Read protocol is outlined in Table 2
while Table 3 outlines the corresponding Byte Write and Byte
Read protocol.The slave receiver address is 11010010 (D2h)
or 11011100 (DCh) depending on state of ADDRSEL.
Pin Description
Pin
Name
PWR
I/O
Description
10
2
BUF_INA,
BUF_INB
VDD2.5
I
Reference input from chipset. 2.5V input.
13,15,20
4,6,24
DDRA[0:2]C
DDRB[0:2]C
VDD2.5
O
Clock outputs. These outputs provide complementary
copies of BUF_INA & BUF_INB, respectively.
12,14,21
3,5,25
DDRA[0:2]T
DDRB[0:2]T
VDD2.5
O
Clock outputs. These outputs provide copies of BUF_INA
& BUF_INB, respectively.
9
1
FB_OUTA
FB_OUTB
VDD2.5
O
Feedback clock for chipset
18
SCLK
VDD2.5
I
SMBus clock input. Has pull-up resistor
19
SDATA
VDD2.5
I/O
SMBus data input. Has pull-up resistor
26
SEL_ADDR
I
Address Select Pin. Has pull-down resistor
7,16,22,28
VDD2.5
2.5V voltage supply
8,11,17,23,27
VSS
Ground
Table 1. Command Code Definition
Bit
Description
7
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
(6:5)
01
(4:0)
Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations, these bits should be '00000'


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