CY28372

Rev 1.0, November 20, 2006

Page 9 of 17

Dial-A-Frequency Feature

SMBus Dial-a-Frequency feature is available in this device via

Byte13 and Byte14. P is a large value PLL constant that

depends on the frequency selection achieved through the

hardware selectors (FS). P value may be determined from the

following table.

PD# (Power-down) Clarification

The PD# (Power-down) pin is used to shut off ALL clocks prior

to shutting off power to the device. PD# is an asynchronous

active LOW input. This signal is synchronized internally to the

device powering down the clock synthesizer. PD# is an

asynchronous function for powering up the system. When PD#

is low, all clocks are driven to a LOW value and held there and

the VCO and PLLs are also powered down. All clocks are shut

down in a synchronous manner so has not to cause glitches

while transitioning to the low ‘stopped’ state.

PD# – Assertion

FS(4:0)

P

00000, 00001, 00010, 00011, 00100, 00101, 11110

127993333

00110, 00111, 10000, 10001, 10010, 10011, 10100

76796000

01000, 01001, 01010, 01011, 01100, 01101, 10101, 10110, 10111, 11001, 11010, 11011,11100, 11101

95995000

01110, 01111, 11000

63996667

11111

191990000

Table 5. Maximum Lumped Capacitive Output Loads

Clock

Max Load

Unit

PCI, PCIF

20

pF

AGP

30

pF

24_48MHz, 48MHz

20

pF

REF

30

pF

IOAPIC

20

pF

CPUT0/CPUC0

See Figure 7

CPUT1

See Figure 7

Figure 1. Power-down Assertion Timing Waveforms

PD#

CPUT0

CPUC0

PCI

REF

USB,24_48MHz

Tri-state

Tri-state