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DS90CF366 Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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DS90CF366 Datasheet(HTML) 3 Page - National Semiconductor (TI) |
3 / 16 page Electrical Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units RECEIVER SUPPLY CURRENT (Figures 2, 3, 4 ) f = 65 MHz 43 60 mA f = 85 MHz 43 70 mA ICCRZ Receiver Supply Current Power Down = Low 140 400 µA Power Down Receiver Outputs Stay Low during Power Down Mode Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. Note 2: Typical values are given for VCC = 3.3V and TA = +25C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and ∆V OD). Receiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Min Typ Max Units CLHT CMOS/TTL Low-to-High Transition Time (Figure 4 ) 2.0 3.5 ns CHLT CMOS/TTL High-to-Low Transition Time (Figure 4 ) 1.8 3.5 ns RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 11, Figure 12 ) f = 85 MHz 0.49 0.84 1.19 ns RSPos1 Receiver Input Strobe Position for Bit 1 2.17 2.52 2.87 ns RSPos2 Receiver Input Strobe Position for Bit 2 3.85 4.20 4.55 ns RSPos3 Receiver Input Strobe Position for Bit 3 5.53 5.88 6.23 ns RSPos4 Receiver Input Strobe Position for Bit 4 7.21 7.56 7.91 ns RSPos5 Receiver Input Strobe Position for Bit 5 8.89 9.24 9.59 ns RSPos6 Receiver Input Strobe Position for Bit 6 10.57 10.92 11.27 ns RSKM RxIN Skew Margin (Note 4) (Figure 13 ) f = 85 MHz 290 ps RCOP RxCLK OUT Period (Figure 5) 11.76 T 50 ns RCOH RxCLK OUT High Time (Figure 5 ) f = 85 MHz 4.5 5 7 ns RCOL RxCLK OUT Low Time (Figure 5) 4.0 5 6.5 ns RSRC RxOUT Setup to RxCLK OUT (Figure 5 ) 2.0 ns RHRC RxOUT Hold to RxCLK OUT (Figure 5 ) 3.5 ns RCCD RxCLK IN to RxCLK OUT Delay @ 25˚C, V CC = 3.3V (Figure 6 ) 5.5 7.0 9.5 ns RPLLS Receiver Phase Lock Loop Set (Figure 7 ) 10 ms RPDD Receiver Power Down Delay (Figure 10 ) 1µs Note 4: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less than 150 ps). www.national.com 3 |
Similar Part No. - DS90CF366_06 |
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Similar Description - DS90CF366_06 |
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