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AD712AQ Datasheet(PDF) 11 Page - Analog Devices

Part No. AD712AQ
Description  Dual Precision, Low Cost, High Speed BiFET Op Amp
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD712
Rev. G | Page 11 of 20
)
SETTLING TIME
OPTIMIZING SETTLING TIME
Most bipolar high speed digital-to-analog converters (DACs)
have current outputs; therefore, for most applications, an
external op amp is required for a current-to-voltage conversion.
The settling time of the converter/op amp combination depends
on the settling time of the DAC and output amplifier. A good
approximation is
() (
2
2
AMP
t
DAC
t
Total
t
S
S
S
+
=
The settling time of an op amp DAC buffer varies with the noise
gain of the circuit, the DAC output capacitance, and the amount
of external compensation capacitance across the DAC output
scaling resistor.
Settling time for a bipolar DAC is typically 100 ns to 500 ns.
Previously, conventional op amps have required much longer
settling times than have typical state-of-the-art DACs; therefore,
the amplifier settling time has been the major limitation to a
high speed, voltage output, digital-to-analog function. The
introduction of the AD71x family of op amps with their 1 μs (to
±0.01% of final value) settling time permits the full high speed
capabilities of most modern DACs to be realized.
In addition to a significant improvement in settling time, the
low offset voltage, low offset voltage drift, and high open-loop
gain of the AD71x family assure 12-bit accuracy over the full
operating temperature range.
The excellent high speed performance of the AD712 is shown in
the oscilloscope photos in Figure 30 and Figure 31. Measure-
ments were taken using a low input capacitance amplifier
connected directly to the summing junction of the AD712 and
both figures show a worst-case situation: full-scale input
transition. The 4 kΩ [10 kΩ||8 kΩ = 4.4 kΩ] output impedance
of the DAC, together with a 10 kΩ feedback resistor, produce an
op amp noise gain of 3.25. The current output from the DAC
produces a 10 V step at the op amp output (0 to −10 V shown in
Figure 30, and −10 V to 0 V shown in Figure 31).
Therefore, with an ideal op amp, settling to ±1/2 LSB (±0.01%)
requires that 375 μV or less appears at the summing junction.
This means that the error between the input and output (that
voltage which appears at the AD712 summing junction) must
be less than 375 μV. As shown in Figure 30, the total settling
time for the AD712/AD565A combination is 1.2 microseconds.
+15V
0.1µF
0.1µF
10pF
OUTPUT
–10V TO +10V
AD565A
–15V
IREF
BIPOLAR
OFFSET ADJUST
IO
0.1µF
R1
100Ω
R2
100Ω
GAIN
ADJUST
REF
IN
REF
GND
–VEE
0.1µF
POWER
GND
MSB
LSB
8kΩ
5kΩ
5kΩ
10V
19.95kΩ
0.5mA
DAC
OUT
10V
SPAN
20V
SPAN
VCC
REF
OUT
BIPOLAR
OFF
9.95kΩ
+
8
4
1/2
AD712
DAC
IOUT = 4 ×
IREF × CODE
20kΩ
Figure 29. ±10 V Voltage Output Bipolar DAC




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