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CY28400OXC-2 Datasheet(PDF) 4 Page - SpectraLinear Inc |
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CY28400OXC-2 Datasheet(HTML) 4 Page - SpectraLinear Inc |
4 / 15 page CY28400-2 Rev 1.0, November 21, 2006 Page 4 of 15 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 1 HIGH_BW# HIGH_BW# 0 = High Bandwidth, 1 = Low bandwidth 1 1 PLL/BYPASS# PLL/BYPASS# 0 = Fanout buffer, 1 = PLL mode 0 1 SRC_DIV2# SRC_DIV2# configures output frequency at half the input frequency 0 = Divided by 2 mode (output = input/2),1 = Normal (output = input) Byte 1: Control Register 1 Bit @pup Name Description 7 1 Reserved Reserved 6 1 OE_6 DIF[T/C]6 Output Enable 0 = Disabled (Tri-state) 1 = Enabled 5 1 OE_5 DIF[T/C]5 Output Enable 0 = Disabled (Tri-state) 1 = Enabled 4 1 Reserved Reserved 3 1 Reserved Reserved 2 1 OE_2 DIF[T/C]2 Output Enable 0 = Disabled (Tri-state) 1 = Enabled 1 1 OE_1 DIF[T/C]1 Output Enable 0 = Disabled (Tri-state) 1 = Enabled 0 1 Reserved Reserved Byte 2: Control Register 2 Bit @pup Name Description 7 0 Reserved Reserved 6 0 SRC_STP_DIF[T/C]6 Allow Control DIF[T/C]6 with assertion of SRC_STP 0 = Free-running 1 = Stopped with SRC_STP 5 0 SRC_STP_DIF[T/C]5 Allow Control DIF[T/C]5 with assertion of SRC_STP 0 = Free-running 1 = Stopped with SRC_STP 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 SRC_STP_DIF[T/C]2 Allow Control DIF[T/C]2 with assertion of SRC_STP 0 = Free-running 1 = Stopped with SRC_STP 1 0 SRC_STP_DIF[T/C]1 Allow Control DIF[T/C]1 with assertion of SRC_STP 0 = Free-running 1 = Stopped with SRC_STP 0 0 Reserved Reserved Byte 0: Control Register 0 (continued) Bit @pup Name Description |
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