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CY28401OC Datasheet(PDF) 4 Page - SpectraLinear Inc |
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CY28401OC Datasheet(HTML) 4 Page - SpectraLinear Inc |
4 / 13 page CY28401 Rev 1.0, November 21, 2006 Page 4 of 13 50 Reserved 40 Reserved 30 Reserved 2 1 HIGH_BW# 0 = High Bandwidth, 1 = Low bandwidth 1 1 PLL/Bypass# 0 = Fanout buffer, 1 = PLL mode 0 1 SRC_DIV/2 0 = Divided by 2 mode, 1 = Normal (output = input) Byte 0: Control Register 0 (continued) Bit @pup Name Description Byte 1: Control Register 1 Bit @pup Name Description 7 1 DIF_7 Output Enable 0 = Disabled (three-state) 1 = Enabled 6 1 DIF_6 Output Enable 0 = Disabled (three-state) 1 = Enabled 5 1 DIF_5 Output Enable 0 = Disabled (three-state) 1 = Enabled 4 1 DIF_4 Output Enable 0 = Disabled (three-state) 1 = Enabled 3 1 DIF_3 Output Enable 0 = Disabled (three-state) 1 = Enabled 2 1 DIF_2 Output Enable 0 = Disabled (three-state) 1 = Enabled 1 1 DIF_1 Output Enable 0 = Disabled (three-state) 1 = Enabled 0 1 DIF_0 Output Enable 0 = Disabled (three-state) 1 = Enabled Byte 2: Control Register 2 Bit @pup Name Description 7 0 Allow Control DIF_7 with assertion of SRC_STOP# 0 = Free-running 1 = Stopped with SRC_STOP# 6 0 Allow Control DIF_6 with assertion of SRC_STOP# 0 = Free-running 1 = Stopped with SRC_STOP# 5 0 Allow Control DIF_5 with assertion of SRC_STOP# 0 = Free-running 1 = Stopped with SRC_STOP# 4 0 Allow Control DIF_4 with assertion of SRC_STOP# 0 = Free-running 1 = Stopped with SRC_STOP# |
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