CY28400-2

Rev 1.0, November 21, 2006

Page 2 of 15

Serial Data Interface

To enhance the flexibility and function of the clock buffer, a

two-signal serial interface is provided. Through the Serial Data

Interface, various device functions, such as individual clock

output buffers, can be individually enabled or disabled. The

registers associated with the Serial Data Interface initialize to

their default setting upon power-up, and therefore use of this

interface is optional. Clock device register changes are

normally made upon system initialization, if any are required.

The interface cannot be used during system operation for

power management functions.

Data Protocol

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operations from the controller. For

block write/read operation, the bytes must be accessed in

sequential order from lowest to highest byte (most significant

bit first) with the ability to stop after any complete byte has

been transferred. For byte write and byte read operations, the

system controller can access individually indexed bytes. The

offset of the indexed byte is encoded in the command code,

as described in

Table 1.

The block write and block read protocol is outlined in

Table 2

while

Table 3 outlines the corresponding byte write and byte

read protocol. The slave receiver address is 11011100 (DCh).

Pin Description

Pin

Name

Type

Description

2,3

SRCT_IN, SRCC_IN

I,DIF

0.7V Differential inputs

6,7;9,10;20,19;

23,22

DIF[T/C][2:1] & [6:5]

O,DIF

0.7V Differential Clock Outputs

8,21

OE_1, OE_6

I,SE

3.3V LVTTL input for enabling differential outputs

Active HIGH if OE_INV = 0

Active LOW if OE_INV = 1

17

HIGH_BW#

I,SE

3.3V LVTTL input for selecting PLL bandwidth

0 = High BW, 1 = Low BW

15

PWRDWN

I,SE

3.3V LVTTL input for Power Down

Active LOW if OE_INV = 0

Active HIGH if OE_INV = 1

16

SRC_STP

I,SE

3.3V LVTTL input for SRC_STP. Disables stoppable outputs.

Active LOW if OE_INV = 0

Active HIGH if OE_INV = 1

13

SCLK

I,SE

SMBus Slave Clock Input

14

SDATA

I/O,OC Open collector SMBus data

26

IREF

I

A precision resistor is attached to this pin to set the differential output

current

12

PLL/BYPASS#

I

3.3V LVTTL input for selecting fan-out or PLL operation

28

VDD_A

PWR

3.3V Power Supply for PLL

27

VSS_A

GND

Ground for PLL

4VSS

GND

Ground for outputs

1,5,11,18,24

VDD

PWR

3.3V power supply for outputs

25

OE_INV

I, SE

Input strap for setting polarity of OE_[7:0], SRC_STP, and PWRDWN

Table 1. Command Code Definition

Bit

Description

7

0 = Block read or block write operation

1 = Byte read or byte write operation

(6:0)

Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be

'0000000'

Table 2. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Bit

Description

Bit

Description

1Start

1Start

2:8

Slave address – 7 bits

2:8

Slave address – 7 bits