CY28408

Rev 1.0, November 20, 2006

Page 8 of 18

Special Functions

PCI_F and IOAPIC Clock Outputs

The PCIF clock outputs are intended to be used, if required,

for systems IOAPIC clock functionality. ANY two of the PCI_F

clock outputs can be used as IOAPIC 33-MHz clock outputs.

They are 3.3V outputs will be divided down via a simple

resistive voltage divider to meet specific system IOAPIC clock

voltage requirements. In the event these clocks are not

required, then these clocks can be used as general PCI clocks

or disabled via the assertion of the PCI_STP# pin.

3V66_1/VCH Clock Output

The 3V66_1/VCH pin has a dual functionality that is selectable

via SMBus. If Byte0, Bit 5 = ‘1’, then the output is configured

as a 48-MHz non-spread spectrum output. This output is

phase aligned with the other 48M outputs (USB and DOT), to

within 1 ns pin-to-pin skew. The switching of 3V66_1/VCH into

VCH mode occurs at system power on. When the SMBus Bit

5 of Byte 0 is programmed from a ‘0’ to a ‘1’, the 3V66_1/VCH

output may glitch while transitioning to 48M output mode.

CPU_STP# Clarification

The CPU_STP# signal is an active LOW input used for

synchronous stopping and starting the CPU output clocks

while the rest of the clock generator continues to function.

CPU_STP# – Assertion

When CPU_STP# pin is asserted, all CPUT/C outputs that are

set with the SMBus configuration to be stoppable via assertion

of CPU_STP# will be stopped after being sampled by two

falling CPUT/C clock edges. The final state of the stopped

CPU signals is CPUT = HIGH and CPU0C = LOW. There is no

change to the output drive current values during the stopped

state. The CPUT is driven HIGH with a current value equal to

(Mult 0 ‘select’) x (Iref), and the CPUC signal will not be driven.

Due to external pull-down circuitry CPUC will be LOW during

this stopped state.

Note:

3. 0 = 10K Pull-down resistor, 1 = 10k Pull-up resistor.

Table 7. Group Timing Relationship and Tolerances

Description

Offset

Tolerance

Conditions

3V66 to PCI

2.5 ns

1.0 ns

3V66 Leads PCI

48M_USB to 48M_DOT Skew

0 or 10.4 ns

1.0 ns

48MUSB

48MDOT

Figure 1. 48M_USB and 48M_DOT Phase Relationship

PCI

PCI_F

Tpci

3V66

Figure 2. 3V66 to PCI and PCI_F Phase Relationship

EPCI3

EPCI1

EPCI(3,1)

0

0

0.0 ns

1

0

0.8 ns

1

1

1.6 ns