CY28409

Rev 1.0, November 22, 2006

Page 8 of 16

Calculating Load Capacitors

In addition to the standard external trim capacitors, trace

capacitance and pin capacitance must also be considered to

correctly calculate crystal loading. As mentioned previously,

the capacitance on each side of the crystal is in series with the

crystal. This means the total capacitance on each side of the

crystal must be twice the specified crystal load capacitance

(CL). While the capacitance on each side of the crystal is in

series with the crystal, trim capacitors (Ce1,Ce2) should be

calculated to provide equal capacitive loading on both sides.

Use the following formulas to calculate the trim capacitor

values for Ce1 and Ce2.

CL....................................................Crystal load capacitance

CLe......................................... Actual loading seen by crystal

using standard value trim capacitors

Ce..................................................... External trim capacitors

Cs .............................................. Stray capacitance (terraced)

Ci ...........................................................Internal capacitance

(lead frame, bond wires etc.)

PD# (Power-down) Clarification

The PD# (Power-down) pin is used to shut off ALL clocks prior

to shutting off power to the device. PD# is an asynchronous

active LOW input. This signal is synchronized internally to the

device powering down the clock synthesizer. PD# is an

asynchronous function for powering up the system. When PD#

is LOW, all clocks are driven to a LOW value and held there

and the VCO and PLLs are also powered down. All clocks are

shut down in a synchronous manner so as not to cause

glitches while changing to the low ‘stopped’ state.

PD# Assertion

When PD# is sampled LOW by two consecutive rising edges

of the CPUC clock then all clock outputs (except CPU) clocks

must be held LOW on their next HIGH-to-LOW transition. CPU

clocks must be held with CPU clock pin driven HIGH with a

value of 2 x Iref and CPUC undriven. Due to the state of

internal logic, stopping and holding the REF clock outputs in

the LOW state may require more than one clock cycle to

complete

XTAL

Ce 2

Ce 1

Cs 1

Cs 2

X1

X2

Ci1

Ci2

Clo c k Ch ip

( C Y 28409)

Tr a c e

2. 8 p F

Tr im

33pF

Pin

3 t o 6p

Figure 2. Crystal Loading Example

Load Capacitance (each side)

Total Capacitance (as seen by the crystal)

Ce = 2 * CL – (Cs + Ci)

Ce1 + Cs1 + Ci1

1

+

Ce2 + Cs2 + Ci2

1

()

1

=

CLe

PD#

3V66, 66MHz

USB, 48MHz

PCI, 33MHz

REF

SRCT 100MHz

SRCC 100MHz

CPUC, 133MHz

CPUT, 133MHz

Figure 3. Power-down Assertion Timing Waveform