CY28412

Rev 1.0, November 20, 2006

Page 9 of 16

PD Deassertion

The power-up latency is less than 1.8 ms. This is the time from

the deassertion of the PD pin or the ramping of the power

supply until the time that stable clocks are output from the

clock chip. All differential outputs stopped in a tristate condition

resulting from power down must be driven high in less than

300

s of PD deassertion to a voltage greater than 200 mV.

After the clock chip’s internal PLL is powered up and locked,

all outputs are enabled within a few clock cycles of each other.

XTAL

Ce2

Ce1

Cs1

Cs2

X1

X2

Ci1

Ci2

Clock Chip

Trace

2.8pF

Trim

33pF

Pin

3 to 6p

Figure 2. Crystal Loading Example

Figure 3. Power-down Assertion Timing Waveform

PD

USB, 48MHz

DOT96T

DOT96C

SRCT 100MHz

SRCC 100MHz

CPUT, 133MHz

PCI, 33 MHz

REF

CPUC, 133MHz