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CY28437ZXCT Datasheet(PDF) 6 Page - SpectraLinear Inc

Part # CY28437ZXCT
Description  Clock Generator for Intel Grantsdale Chipset
Download  22 Pages
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Manufacturer  SPECTRALINEAR [SpectraLinear Inc]
Direct Link  http://www.spectralinear.com
Logo SPECTRALINEAR - SpectraLinear Inc

CY28437ZXCT Datasheet(HTML) 6 Page - SpectraLinear Inc

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CY28437
Rev 1.0, November 20, 2006
Page 6 of 22
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
1
PCI5
PCI5 Output Enable
0 = Disabled, 1 = Enabled
6
1
PCI4
PCI4 Output Enable
0 = Disabled, 1 = Enabled
5
1
PCI3
PCI3 Output Enable
0 = Disabled, 1 = Enabled
4
1
PCI2
PCI2 Output Enable
0 = Disabled, 1 = Enabled
3
1
PCI1
PCI1 Output Enable
0 = Disabled, 1 = Enabled
2
1
PCI0
PCI0 Output Enable
0 = Disabled, 1 = Enabled
1
1
RESERVED
RESERVED, Set = 1
0
1
PCIF1
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
Byte 3: Control Register 3
Bit
@Pup
Name
Description
7
0
SRC[T/C]7
Allow control of SRC[T/C]7 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
6
0
SRC[T/C]6
Allow control of SRC[T/C]6 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
5
0
SRC[T/C]5
Allow control of SRC[T/C]5 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
4
0
SRC[T/C]4_SATA
Allow control of SRC[T/C]4_SATA with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
3
0
SRC[T/C]3
Allow control of SRC[T/C]3 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
2
0
SRC[T/C]2
Allow control of SRC[T/C]2 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
1
0
SRC[T/C]1
Allow control of SRC[T/C]1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
0
0
SRC[T/C]0
Allow control of SRC[T/C]0 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Byte 4: Control Register 4
Bit
@Pup
Name
Description
7
HW
FS_E
FS_E Reflects the value of the FS_E pin sampled on power-up. 0 = FS_E
was LOW during VTT_PWRGD# assertion.
6
0
DOT96
DOT_PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
5
0
RESERVED
RESERVED, Set = 0
4
0
PCIF1
Allow control of PCIF1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
3
0
PCIF0
Allow control of PCIF0 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
2
1
RESERVED
RESERVED, Set = 1
1
1
RESERVED
RESERVED, Set = 1
0
1
RESERVED
RESERVED, Set = 1


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