CY28442 datasheet(8/21 Pages) SPECTRALINEAR

Part #	CY28442

Description	Clock Generator for Intel Alviso Chipset

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Manufacturer	SPECTRALINEAR [SpectraLinear Inc]

Direct Link	http://www.spectralinear.com

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CY28442

Rev 1.0, November 21, 2006

Page 8 of 21

3

0

RESERVED

2

1

CLKREQ#A

SRC[T/C]4 CLKREQ#A control

1 = SRC[T/C]4 stoppable by CLKREQ#A pin

0 = SRC[T/C]4 not controlled by CLKREQ#A pin

1

0

CLKREQ#A

SRC[T/C]2 CLKREQ#A control

1 = SRC[T/C]2 stoppable by CLKREQ#A pin

0 = SRC[T/C]2 not controlled by CLKREQ#A pin

0

RESERVED

Byte 9: Control Register 9

Bit

@Pup

Name

Description

70

S3

96_100_SSC Spread Spectrum Selection table:

S[3:0] SS%

‘0000’ = -0.8%(Default value)

‘0001’ = -1.0%

‘0010‘ = -1.25%

‘0011‘ = -1.5%

‘0100‘ = -1.75%

‘0101‘ = -2.0%

‘0110‘ = -2.5%

‘0111‘ = -0.5%

‘1000‘ = ± 0.25%

‘1001‘ = ± 0.4%

‘1010‘ = ± 0.5%

‘1011‘ = ± 0.6%

‘1100‘ = ± 0.8%

‘1101‘ = ± 1.0%

‘1110‘ = ± 1.25%

‘1111‘ = ± 1.5%

60

S2

50

S1

40

S0

3

1

96_100 SEL

Software select 96_100_SSC output frequency , 0 = 96MHz , 1 = 100MHz.

2

1

96_100 Enable

96_100_SSC Enable , 0 = Disable , 1 = Enable.

1

96_100 SS Enable

96_100_SSC Spread spectrum enable. 0 = Disable , 1 = Enable.

0

96_100 SW HW

Select output frequency of 96_100_SSC via software or hardware

0 = Hardware, 1 = Software.

Byte 10: Control Register 10

Bit

@Pup

Name

Description

7

0

RESERVED

6

0

CLKREQ#B

SRC[T/C]4 CLKREQ#B control

1 = SRC[T/C]4 stoppable by CLKREQ#B pin

0 = SRC[T/C]4not controlled by CLKREQ#B pin

5

0

CLKREQ#B

SRC[T/C]2 CLKREQ#B control

1 = SRC[T/C]2 stoppable by CLKREQ#B pin

0 = SRC[T/C]2 not controlled by CLKREQ#B pin

4

0

RESERVED

3

0

CLKREQ#A

SRC[T/C]7CLKREQ#A control

1 = SRC[T/C]7 stoppable by CLKREQ#A pin

0 = SRC[T/C]7 not controlled by CLKREQ#A pin

Byte 8: Control Register 8 (continued)

Bit

@Pup

Name

Description

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