Rev 1.0, November 28, 2006

Page 8 of 8

W48C101-01

While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir-

cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in

normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica-

tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional

processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any

circuitry or specification without notice.

48-MHz Clock Outputs (Lump Capacitance Test Load = 20 pF = 66.6/100 MHz)

Parameter

Description

Test Condition/Comments

CPU = 66.6/100 MHz

Unit

Min.

Typ.

Max.

f

Frequency, Actual

Determined by PLL divider ratio (see m/n below)

48.008

MHz

Deviation from 48 MHz

(48.008 – 48)/48

+167

ppm

m/n

PLL Ratio

(14.31818 MHz x 57/17 = 48.008 MHz)

57/17

Output Rise Edge Rate

Measured from 0.4V to 2.4V

1

4

V/ns

Output Fall Edge Rate

Measured from 2.4V to 0.4V

1

4

V/ns

Duty Cycle

Measured on rising and falling edge at 1.5V

45

55

%

Frequency Stabilization

from Power-up (cold start)

Assumes full supply voltage reached within 1 ms

from power-up. Short cycles exist prior to

frequency stabilization.

3ms

AC Output Impedance

Average value during switching transition. Used

for determining series termination value.

25

Ordering Information

Ordering Code

Freq. Mask

Code

Package

Name

Package Type

W48C101

-01

H

48-pin SSOP (300 mils)

Package Diagram

48-Lead Shrunk Small Outline Package O48