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W305B Datasheet(PDF) 7 Page - SpectraLinear Inc |
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W305B Datasheet(HTML) 7 Page - SpectraLinear Inc |
7 / 20 page W305B Rev 1.0, November 20, 2006 Page 7 of 20 W305B Serial Configuration Map The serial bits will be read by the clock driver in the following order: Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N – Bits 7, 6, 5, 4, 3, 2, 1, 0 All unused register bits (reserved and N/A) should be written to a “0” level. All register bits labeled “Initialize to 0” must be written to zero during initialization. 29 Acknowledge from slave 30:37 Data byte from slave – 8 bits 38 Not Acknowledge 39 Stop Table 4. Byte Read and Byte Write Protocol (continued) Byte Write Protocol Byte Read Protocol Bit Description Bit Description Byte 0: Control Register 0 Bit Pin# Name Default Description Bit 7 - SEL4 0 See Table 5 Bit 6 - SEL3 0 See Table 5 Bit 5 - SEL2 0 See Table 5 Bit 4 - SEL1 0 See Table 5 Bit 3 - SEL0 0 See Table 5 Bit 2 - Spread Select2 0 ‘000’ = Normal (spread off) ‘001’ = Test Mode ‘010’ = Reserved ‘011’ = Three-Stated ‘100’ = –0.5% ‘101’ = ±0.5% ‘110’ = ±0.25% ‘111’ = ±0.38% Bit 1 - Spread Select1 0 Bit 0 - Spread Select0 0 Byte 1: Control Register 1 Bit Pin# Name Default Description Bit 7 23 Latched FS4 input X Latched FS[4:0] inputs. These bits are read only. Bit 6 3 Latched FS3 input X Bit 5 13 Latched FS2 input X Bit 4 12 Latched FS1 input X Bit 3 11 Latched FS0 input X Bit 2 - Reserved 0 Reserved Bit 1 3 REF2X 1 (Active/Inactive) Bit 0 - Reserved 0 Reserved Byte 2: Control Register 2 Bit Pin# Name Default Description Bit 7 20 PCI7 1 (Active/Inactive) Bit 6 19 PCI6 1 (Active/Inactive) Bit 5 18 PCI5 1 (Active/Inactive) Bit 4 16 PCI4 1 (Active/Inactive) |
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