W320-03

Rev 1.0, November 25, 2006

Page 2 of 16

Pin Summary

Name

Pins

Description

REF

56

3.3V 14.318 MHz clock output

XTAL_IN

2

14.318 MHz crystal input

XTAL_OUT

3

14.318 MHz crystal input

CPU, CPU# [0:2]

44, 45, 48, 49, 51,

52

Differential CPU clock outputs

3V66_0

33

3.3V 66 MHz clock output

3V66_1/VCH

35

3.3V selectable through SMBus to be 66 MHz or 48 MHz

66IN/3V66_5

24

66 MHz input to buffered 66BUFF and PCI or 66 MHz clock from internal VCO

66BUFF [2:0] /3V66

[4:2]

21, 22, 23

66 MHz buffered outputs from 66Input or 66 MHz clocks from internal VCO

PCI_F [0:2]

5, 6, 7,

33 MHz clocks divided down from 66Input or divided down from 3V66

PCI [0:6]

10, 11, 12, 13, 16,

17, 18

PCI clock outputs divided down from 66Input or divided down from 3V66

USB

39

Fixed 48 MHz clock output

DOT

38

Fixed 48 MHz clock output

S2

40

Special 3.3V 3 level input for Mode selection

S1, S0

54, 55

3.3V LVTTL inputs for CPU frequency selection

IREF

42

A precision resistor is attached to this pin which is connected to the internal

current reference

MULT0

43

3.3V LVTTL input for selecting the current multiplier for the CPU outputs

PWR_DWN#

25

3.3V LVTTL input for Power_Down# (active LOW)

PCI_STOP#

34

3.3V LVTTL input for PCI_STOP# (active LOW)

CPU_STOP#

53

3.3V LVTTL input for CPU_STOP# (active LOW)

PWRGD#

28

3.3V LVTTL input is a level sensitive strobe used to determine when S[2:0] and

MULTI0 inputs are valid and OK to be sampled (Active LOW). Once PWRGD#

is sampled LOW, the status of this output will be ignored.

SDATA

29

SMBus compatible SDATA

SCLK

30

SMBus compatible Sclk

VDD_REF, VDD_PCI,

VDD_3V66,

VDD_CPU

1, 8, 14, 19, 32, 46,

50

3.3V power supply for outputs

VDD_48 MHz

37

3.3V power supply for 48 MHz

VDD_CORE

26

3.3V power supply for PLL

GND_REF, GND_PCI,

GND_3V66,

GND_IREF,

VDD_CPU

4, 9, 15, 20, 31, 36,

41, 47

Ground for outputs

GND_CORE

27

Ground for PLL