CP82C82 datasheet(1/7 Pages) INTERSIL

Part #	CP82C82

Description	CMOS Octal Latching Bus Driver

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Manufacturer	INTERSIL [Intersil Corporation]

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274

TM

March 1997

82C82

CMOS Octal Latching Bus Driver

Features

• Full Eight-Bit Parallel Latching Buffer

• Bipolar 8282 Compatible

• Three-State Noninverting Outputs

• Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max.

• Gated Inputs:

- Reduce Operating Power

- Eliminate the Need for Pull-Up Resistors

• Single 5V Power Supply

• Low Power Operation . . . . . . . . . . . . . . . ICCSB = 10

µA

• Operating Temperature Ranges

- C82C82 . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC

- I82C82 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC

- M82C82 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC

Description

The Intersil 82C82 is a high performance CMOS Octal

Latching Buffer manufactured using a self-aligned silicon

gate CMOS process (Scaled SAJI IV). The 82C82 provides

an eight-bit parallel latch/buffer in a 20 pin package. The

active high strobe (STB) input allows transparent transfer of

data and latches data on the negative transition of this sig-

nal. The active low output enable (OE) permits simple inter-

face to state-of-the-art microprocessor systems.

Ordering Information

PART NUMBER

TEMP. RANGE

PACKAGE

PKG. NO.

CP82C82

0oC to +70oC

20 Ld PDIP

E20.3

IP82C82

-40oC to +85oC

CS82C82

0oC to +70oC

20 Ld PLCC

N20.35

IS82C82

-40oC to +85oC

CD82C82

0oC to +70oC

20 Ld CERDIP

F20.3

ID82C82

-40oC to +85oC

MD82C82/B

-55oC to +125oC

8406701RA

SMD #

MR82C82/B

-55oC to +125oC 20 Pad CLCC

J20.A

84067012A

SMD #

Pinouts

82C82 (PDIP, CERDIP)

TOP VIEW

82C82 (PLCC, CLCC)

TOP VIEW

11

12

13

14

15

16

17

18

20

19

10

9

8

7

6

5

4

3

2

1

DI0

DI1

DI2

DI3

DI4

DI5

DI7

DI6

OE

GND

VCC

DO1

DO2

DO3

DO0

DO4

DO5

DO6

DO7

STB

19

3

2

20

1

15

16

17

18

14

910

11

12

13

4

5

6

7

8

DI4

DI5

DI6

DI7

DI3

DO2

DO3

DO4

DO5

DO1

TRUTH TABLE

STB

OE

DI

DO

XH

X

Hi-Z

HL

L

HL

H

↓

LX

†

H

= Logic One

L

= Logic Zero

X

= Don’t Care

†

= Latched to Value of Last

Data

Hi-Z

= High Impedance

↓

= Neg. Transition

PIN NAMES

DESCRIPTION

DI0-DI7

Data Input Pins

DO0-DO7

Data Output Pins

STB

Active High Strobe

OE

Active Low Output

Enable

FN2975.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a trademark of Intersil Americas Inc.

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