11

FN7000.3

May 4, 2007

where:

•

θ

The maximum power dissipation actually produced by an IC

is the total quiescent supply current times the total power

supply voltage, plus the power in the IC due to the loads, or:

P

DMAX

ΣiV

S

I

SMAX

V

S

(

+ - V

I

×

+

×

[]

×

=

when sourcing, and:

P

DMAX

ΣiV

S

I

SMAX

V

OUT

(

i - V

I

×

+

×

[]

×

=

when sinking.

where:

and 28 provide a convenient way to see if the device will

overheat. The maximum safe power dissipation can be

found graphically, based on the package type and the

ambient temperature. By using the previous equation, it is a

derating curves. To ensure proper operation, it is important

to observe the recommended derating curves in Figures 27

and 28.

JEDEC JESD51-3 LOW EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

0.6

0.4

0.3

0.2

0.1

0

0

255075

100

125

AMBIENT TEMPERATURE (°C)

85

486mW

θ

20

6°C

/W

M

SO

P1

0

0.5

θ

20

6°C

/W

M

SO

P1

0

FIGURE 27.

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

1

0.9

0.6

0.4

0.3

0.2

0.1

0

0

255075

100

125

AMBIENT TEMPERATURE (°C)

85

870mW

θ

11

5°C

/W

M

SO

P1

0

0.8

0.5

0.7

PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

FIGURE 28. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

Power Supply Bypassing and Printed Circuit

Board Layout

The EL5128 can provide gain at high frequency. As with any

high-frequency device, good printed circuit board layout is

necessary for optimum performance. Ground plane

construction is highly recommended, lead lengths should be

as short as possible and the power supply pins must be well

bypassed to reduce the risk of oscillation. For normal single

connected in parallel, placed in the region of the amplifier.

One 4.7µF capacitor may be used for multiple devices. This

same capacitor combination should be placed at each

supply pin to ground if split supplies are to be used.

EL5128