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HSP45116AVC-52 Datasheet(PDF) 10 Page - Intersil Corporation |
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HSP45116AVC-52 Datasheet(HTML) 10 Page - Intersil Corporation |
10 / 19 page 10 FN4156.4 May 7, 2007 The Phase Accumulator consists of registers and adders that compute the value of the current phase at every clock. It has three inputs: Center Frequency, which corresponds to the carrier frequency of a signal; Offset Frequency, which is the deviation from the Center Frequency; and Phase, which is a 16-bit number that is added to the current phase for PSK modulation schemes. These three values are used by the Phase Accumulator and Phase Adder to form the phase of the internally generated sine and cosine. The sum of the values in Center and Offset Frequency Registers corresponds to the desired phase increment (modulo 232) from one clock to the next. For example, loading both registers with zero will cause the Phase Accumulator to add zero to its current output; the output of the PFCS will remain at its current value; i.e., the output of the NCOM will be a DC signal. If a hexadecimal 00000001 is loaded into the Center Frequency Control Register, the output of the PFCS will increment by one after every clock. This will step through every location in the Sine/Cosine Generator, so that the output will be the lowest frequency above DC that can be generated by the NCOM, i.e., the clock frequency divided by 232. If the input to the Center Frequency Control Register is hex 80000000, the PFCS will step through the Generator with half of the maximum step size, so that frequency of the output waveform will be half of the sample rate. The operation of the Offset Frequency Control Register is identical to that of the Center Frequency Control Register; having two separate registers allows the user to generate an FM signal by loading the carrier frequency in the Center Frequency Control Register and updating the Offset Frequency Control Register with the value of the frequency offset - the difference between the carrier frequency and the frequency of the output signal. A logic low on CLROFR disables the output of the Offset Frequency Register without clearing the contents of the register. TABLE 2. MOD0-1 DECODE MOD1 MOD0 PHASE SHIFT (DEGREES) 0 0 0 0 1 90 1 0 270 1 1 180 Initializing the Phase Accumulator Register is done by putting a low on the LOAD line. This zeroes the feedback path to the accumulator, so that the register is loaded with the current value of the phase increment summer on the next clock. The final phase value going to the Generator can be adjusted using MODPI/2PI to force the range of the phase to be 0o to 180o (modulo π) or 0o to 360o (modulo 2π). Modulo 2 π is the mode used for modulation, demodulation, direct digital synthesis, etc. Modulo π is used to calculate FFTs. This is explained in greater detail in the Applications Section. The Phase Register adds an offset to the output of the Phase Accumulator. Since the Phase Register is only 16 bits, it is added to the top 16 bits of the Phase Accumulator. The Time Accumulator consists of a register which is incremented on every clock. The amount by which it increments is loaded into the Input Registers and is latched into the Time Accumulator Register on rising edges of CLK while ENTIREG is low. The output of the Time Accumulator is the accumulator carry out, TICO. TICO can be used as a timer to enable the periodic sampling of the output of the NCOM. The number programmed into this register equals 232 x CLK period/desired time interval. TICO is disabled and its phase is initialized by zeroing the feedback path of the accumulator with RBYTILD. Sine/Cosine Section The Sine/Cosine Section (Figure 2) converts the output of the PFCS into the appropriate values for the sine and cosine. It takes the most significant 20 bits of the PFCS output and passes them through a look up table to form the 16-bit sine and cosine inputs to the CMAC. CLK SINE/COSINE GENERATOR 20 32 32 REG CLK R.RBYTILD MUX COS 16 SIN 16 16 16 16 16 FIGURE 2. SINE/COSINE SECTION The 20-bit word maps into 2 π radians so that the angular resolution is 2 π/220. An address of zero corresponds to 0 radians and an address of hex FFFFF corresponds to 2 π- (2π/220) radians. The outputs of the Generator Section are 2’s complement sine and cosine values. The sine and cosine outputs range from hexadecimal 8001, which represents negative full scale to 7FFF, which represents positive full scale. Note that the normal range for two’s complement numbers is 8000 to 7FFF; the output range of the SIN/COS generator is scaled by one so that it is symmetric about 0. The sine and cosine values are computed to reduce the amount of ROM needed. The magnitude of the error in the computed value of the complex vector is less than -90.2dB. The error in the sine or cosine alone is approximately 2dB better. If RBYTILD is low, the output of the PFCS goes directly to the inputs of the CMAC. If the real and imaginary inputs of the CMAC are programmed to hex 7FFF and 0 respectively, then the output of the PFCS will appear on output bits 0 HSP45116A |
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