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5962-9054902MQA Datasheet(PDF) 5 Page - Intersil Corporation |
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5962-9054902MQA Datasheet(HTML) 5 Page - Intersil Corporation |
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5 / 16 page  5 Encoder Operation The Encoder requires a single clock with a frequency of twice the desired data rate applied at the SEND CLOCK input. An auxiliary divide by six counter is provided on chip which can be utilized to produce the SEND CLOCK by divid- ing the DECODER CLOCK. The frame length is set by pro- gramming the COUNT inputs. Parity is selected by programming ENCODER PARITY SELECT high for odd par- ity or low for even parity. The Encoder’s cycle begins when ENCODER ENABLE is high during a falling edge of ENCODER SHIFT CLOCK . This cycle lasts for one word length or K + 4 ENCODER SHIFT CLOCK periods, where K is the number of bits to be sent. At the next low-to-high transition of the ENCODER SHIFT CLOCK, a high SYNC SELECT input actuates a Command sync or a low will produce a Data sync for the word . When the Encoder is ready to accept data, the SEND DATA output will go high for K ENCODER SHIFT CLOCK periods . During these K periods the data should be clocked into the SERIAL DATA input with every high-to- low transition of the ENCODER SHIFT CLOCK - so it can be sampled on the low-to-high transition. After the sync and Manchester II encoded data are transmitted through the BIPOLAR ONE and BIPOLAR ZERO outputs, the Encoder adds on an additional bit with the parity for that word . If ENCODER ENABLE is held high continuously, consecutive words will be encoded without an interframe gap. ENCODER ENABLE must go low by time (as shown) to prevent a consecutive word from being encoded. At any time a low on OUTPUT INHIBIT input will force both bipolar out- puts to a high state but will not affect the Encoder in any other way. To abort the Encoder transmission, a positive pulse must be applied at MASTER RESET. Any time after or during this pulse, a low-to-high transition on SEND CLOCK clears the internal counters and initializes the Encoder for a new word. Decoder Operation To operate the Decoder asynchronously requires a single clock with a frequency of 12 times the desired data rate applied at the DECODER CLOCK input. To operate the Decoder synchronously requires a SYNCHRONOUS CLOCK at a frequency 2 times the data rate which is syn- chronized with the data at every high-to-low transition applied to the SYNCHRONOUS CLK input. The Manchester II coded data can be presented to the Decoder asynchro- nously in one of two ways. The BIPOLAR ONE and BIPOLAR ZERO inputs will accept data from a comparator sensed transformer coupled bus as specified in Military Spec 1553. The UNIPOLAR DATA input can only accept nonin- verted Manchester II coded data. (e.g., from BIPOLAR ONE OUT on an Encoder through an inverter to Unipolar Data Input). The Decoder is free running and continuously monitors its data input lines for a valid sync character and two valid Manchester data bits to start an output cycle. When a valid sync is recognized , the type of sync is indicated by a high level at either COMMAND SYNC or DATA SYNC output. If the sync character was a command sync the COMMAND SYNC output will go high and remain high for K SHIFT CLOCK periods , where K is the number of bits to be received. If the sync character was a data sync, the DATA SYNC output will go high. The TAKE DATA output will go high and remain high - while the Decoder is transmit- 1 2 4 3 4 5 5 FIGURE 1. ENCODER SEND CLOCK BIT K-1 BIT K-3 BIT K-4 BIT K-5 BIT 4 BIT K-2 MSB BIT 3 BIT 2 BIT 1 PARITY BIT 1 BIT 2 BIT 3 BIT 4 BIT 4 BIT 3 BIT 2 BIT 1 PARITY 1ST HALF 2ND HALF MSB BIT K-1 BIT K-2 BIT K-3 BIT K-4 SYNC SYNC MSB BIT K-1 4 5 3 2 1 VALID TIMING 0 1 2 3 4 5 6 7 N-3 N-2 N-1 N N-4 ENCODER SHIFT CLOCK ENCODER ENABLE SYNC SELECT SEND DATA SERIAL DATA IN BIPOLAR ONE OUT BIPOLAR ZERO OUT DON’T CARE DON’T CARE BIT K-2 BIT K-3 BIT K-4 1 2 3 2 3 HD-15531 |
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