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DS15MB200 Datasheet(PDF) 9 Page - National Semiconductor (TI) |
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DS15MB200 Datasheet(HTML) 9 Page - National Semiconductor (TI) |
9 / 10 page Interfacing LVDS to LVPECL An LVDS driver consists of a current source (nominal 3.5mA) which drives a CMOS differential pair. It needs a differential resistive load in the range of 70 to 130 ohms to generate LVDS levels. In a system, the load should be selected to match transmission line characteristic differential impedance so that the line is properly terminated. The termination resis- tor should be placed as close to the receiver inputs as possible. When interfacing an LVDS driver with a non-LVDS receiver, one only needs to bias the LVDS signal so that it is within the common mode range of the receiver. This may be done by using separate biasing voltage which demands another power supply. Some receivers have required biasing voltage available on-chip (V T,VTT or VBB). Figure 4 illustrates interface between an LVDS driver and a LVPECL with a V T pin available. R1 and R2, if not present in the receiver (Note 16), provide proper resistive load for the driver and termination for the transmission line, and V T sets desired bias for the receiver. Figure 5 illustrates AC coupled interface between an LVDS driver and LVPECL receiver without a V T pin available. The resistors R1, R2, R3, and R4, if not present in the receiver (Note 16), provide a load for the driver, terminate the trans- mission line, and bias the signal for the receiver. Note 16: The bias networks shown above for LVPECL drivers and receivers may or may not be present within the driver device. The LVPECL driver and receiver specification must be reviewed closely to ensure compatibility be- tween the driver and receiver terminations and common mode operating ranges. Packaging Information The Leadless Leadframe Package (LLP) is a leadframe based chip scale package (CSP) that may enhance chip speed, reduce thermal impedance, and reduce the printed circuit board area required for mounting. The small size and very low profile make this package ideal for high density PCBs used in small-scale electronic applications such as cellular phones, pagers, and handheld PDAs. The LLP pack- age is offered in the no Pullback configuration. In the no Pullback configuration the standard solder pads extend and terminate at the edge of the package. This feature offers a visible solder fillet after board mounting. The LLP has the following advantages: • Low thermal resistance • Reduced electrical parasitics • Improved board space efficiency • Reduced package height • Reduced package mass For more details about LLP packaging technology, refer to applications note AN-1187, "Leadless Leadframe Package" 20157363 FIGURE 4. DC Coupled LVDS to LVPECL Interface 20157364 FIGURE 5. AC Coupled LVDS to LVPECL Interface www.national.com 9 |
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