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EL5256IY-T7 Datasheet(PDF) 11 Page - Intersil Corporation |
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EL5256IY-T7 Datasheet(HTML) 11 Page - Intersil Corporation |
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11 / 17 page  11 FN7386.5 September 13, 2007 determine if load conditions or package types need to be modified to assure operation of the amplifier in a safe operating area. The maximum power dissipation allowed in a package is determined according to Equation 2: Where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature θ JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: For sourcing: For sinking: Where: VS = Supply voltage ISMAX = Maximum quiescent supply current VOUT = Maximum output voltage of the application RLOAD = Load resistance tied to ground ILOAD = Load current N = number of amplifiers (max = 2) By setting the two PDMAX equations equal to each other, we can solve the output current and RLOAD to avoid the device overheat. Power Supply Bypassing Printed Circuit Board Layout As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as short as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to the ground plane, a single 4.7µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor from VS+ to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the VS- pin becomes the negative supply rail. See Figure 37 for a complete tuned power supply bypass methodology. Printed Circuit Board Layout For good AC performance, parasitic capacitance should be kept to a minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier's inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces. PD MAX T JMAX T AMAX – Θ JA --------------------------------------------- = (EQ. 2) PD MAX V S I SMAX V S V OUTi – () i1 = n ∑ V OUTi R Li ----------------- × + × = (EQ. 3) PD MAX V S I SMAX V OUTi V S – () i1 = n ∑ I LOADi × + × = (EQ. 4) EL5156, EL5157, EL5256, EL5257 |
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