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DS90CR288AMTD Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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DS90CR288AMTD Datasheet(HTML) 11 Page - National Semiconductor (TI) |
11 / 16 page AC Timing Diagrams (Continued) DS90CR287 MTD56 (TSSOP) Package Pin Description — Channel Link Transmitter Pin Name I/O No. Description TxIN I 28 TTL level input. TxOUT+ O 4 Positive LVDS differential data output. TxOUT− O 4 Negative LVDS differential data output. TxCLK IN I 1 TTL level clock input. The rising edge acts as data strobe. Pin name TxCLK IN. See Applications Information section. TxCLK OUT+ O 1 Positive LVDS differential clock output. TxCLK OUT− O 1 Negative LVDS differential clock output. PWR DOWN I 1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down. See Applications Information section. V CC I 4 Power supply pins for TTL inputs. GND I 5 Ground pins for TTL inputs. PLL V CC I 1 Power supply pin for PLL. PLL GND I 2 Ground pins for PLL. LVDS V CC I 1 Power supply pin for LVDS outputs. LVDS GND I 3 Ground pins for LVDS outputs. DS90CR288A MTD56 (TSSOP) Package Pin Description — Channel Link Receiver Pin Name I/O No. Description RxIN+ I 4 Positive LVDS differential data inputs. RxIN− I 4 Negative LVDS differential data inputs. RxOUT O 28 TTL level data outputs. RxCLK IN+ I 1 Positive LVDS differential clock input. RxCLK IN− I 1 Negative LVDS differential clock input. RxCLK OUT O 1 TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT. PWR DOWN I 1 TTL level input. When asserted (low input) the receiver outputs are low. V CC I 4 Power supply pins for TTL outputs. 10108720 C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos — Transmitter output pulse position (min and max) RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)(Note 7) + ISI (Inter-symbol interference)(Note 8) Cable Skew — typically 10 ps–40 ps per foot, media dependent Note 7: Cycle-to-cycle jitter is less than 150ps at 85MHz. Note 8: ISI is dependent on interconnect length; may be zero FIGURE 16. Receiver LVDS Input Skew Margin www.national.com 11 |
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