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DS3502U+ Datasheet(PDF) 8 Page - Maxim Integrated Products |
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DS3502U+ Datasheet(HTML) 8 Page - Maxim Integrated Products |
8 / 10 page High-Voltage, NV, I2C POT 8 _______________________________________________________________________________________ data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses, including when it is reading bits from the slave. Acknowledge (ACK and NACK): An Acknowledge (ACK) or Not Acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a 0 during the 9th bit. A device performs a NACK by trans- mitting a 1 during the 9th bit. Timing for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or indicates that the device is not receiving data. Byte write: A byte write consists of 8 bits of information transferred from the master to the slave (most signifi- cant bit first) plus a 1-bit acknowledgment from the slave to the master. The 8 bits transmitted by the mas- ter are done according to the bit write definition and the acknowledgment is read using the bit read definition. Byte read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to ter- minate communication so the slave will return control of SDA to the master. Slave address byte: Each slave on the I2C bus responds to a slave address byte sent immediately fol- lowing a START condition. The slave address byte con- tains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. The slave address byte of the DS3502 is shown in Figure 1. When the R/W bit is 0 (such as in 50h), the master is indicating it will write data to the slave. If R/W = 1 (51h in this case), the master is indicating it wants to read from the slave. If an incorrect slave address is written, the DS3502 assumes the master is communicating with another I2C device and ignores the communication until the next START condition is sent. Memory address: During an I2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte trans- mitted during a write operation following the slave address byte. I2C Communication Writing a single byte to a slave: The master must gen- erate a START condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a STOP condition. Remember the master must read the slave’s acknowledgment during all byte write operations. When writing to the DS3502, the potentiometer adjusts to the new setting once it has acknowledged the new data that is being written, and the EEPROM is written following the STOP condition at the end of the write command. To change the setting without changing the EEPROM, termi- nate the write with a repeated START condition before the next STOP condition occurs. Using a repeated START condition prevents the tW delay required for the EEPROM write cycle to finish. Acknowledge polling: Any time a EEPROM byte is written, the DS3502 requires the EEPROM write time (tW) after the STOP condition to write the contents of the byte to EEPROM. During the EEPROM write time, the device will not acknowledge its slave address because it is busy. It is possible to take advantage of this phenomenon by repeatedly addressing the DS3502, which allows communication to continue as soon as the DS3502 is ready. The alternative to acknowledge polling is to wait for a maximum period of tW to elapse before attempting to access the device. EEPROM write cycles: The DS3502’s EEPROM write cycles are specified in the Nonvolatile Memory Characteristics table. The specification shown is at the worst-case temperature (hot) as well as at room tem- perature. Writing to the WR/IVR register with MODE = 1 does not count as a EEPROM write. Reading a single byte from a slave: Unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read opera- tion occurs at the present value of the memory address counter. To read a single byte from the slave, the master generates a START condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a STOP condition. However, since requiring the master to keep track of the memory address counter is impractical, the following method should be used to perform reads from a specified memory location. |
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