HM628512 Series

9

Write Cycle

HM628512

-5

-7A

-7

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

Notes

Write cycle time

t

WC

55

—

55

—

70

—

ns

Chip selection to end of write

t

CW

50

—

50

—

60

—

ns

2

Address setup time

t

AS

0—

0—

0—

ns

3

Address valid to end of write

t

AW

50

—

50

—

60

—

ns

Write pulse width

t

WP

40

—

40

—

50

—

ns

1, 8

Write recovery time

t

WR

5—

5—

5—

ns

4

WE to output in high-Z

t

WHZ

0

20

0

20

0

25

ns

5, 6, 7

Data to write time overlap

t

DW

25

—

25

—

30

—

ns

Data hold from write time

t

DH

0—

0—

0—

ns

Output active from output in high-Z

t

OW

5—

5—

5—

ns

6

Output disable to output in high-Z

t

OHZ

0

20

0

20

0

25

ns

5, 6

Notes: 1. A write occurs during the overlap (t

A write begins at the later

transition of

CS going low or WE going low. A write ends at the earlier transition of CS going high

or

WE going high. t

2. t

3. t

4. t

5. During this period, I/O pins are in the output state so that the input signals of the opposite phase to

the outputs must not be applied.

6. This parameter is sampled and not 100% tested.

7. t

referred to output voltage levels.

8. In the write cycle with

OE low fixed, t

data bus contention. t