CY7C344
CY7C344B
5
External Synchronous Switching Characteristics[7] Over Operating Range (continued)
7C344B–10
7C344B–12
7C344–15
7C344B–15
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fMAX2
Maximum Frequency with Internal Only Feed-
back (1/(tCF + tS))
[4, 15]
Com’l/Ind
111.1
90.9
71.4
MHz
Mil
90.9
71.4
fMAX3
Data Path Maximum Frequency, least of 1/(tWL
+ tWH), 1/(tS + tH), or (1/tCO1)
[4, 16]
Com’l/Ind
125.0
111.1
83.3
MHz
Mil
111.1
83.3
fMAX4
Maximum Register Toggle Frequency 1/(tWL +
tWH)
[4, 17]
Com’l/Ind
125.0
111.1
83.3
MHz
Mil
111.1
83.3
tOH
Output Data Stable Time from Synchronous
Clock Input[4, 18]
Com’l/ Ind
3
3
3
ns
Mil
3
3
Shaded area contains preliminary information.
Notes:
8.
This parameter is the delay from an input signal applied to a dedicated input pin to a combinatorial output on any output pin. This delay assumes no expander
terms are used to form the logic function.
9.
This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to
form the logic function.
10. This parameter is the delay associated with an input signal applied to a dedicated input pin to combinatorial output on any output pin. This delay assumes
expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter
is tested periodically by sampling production material.
11.
This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output pin. This delay assumes expander terms are used
to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by
sampling production material.
12. This specification is a measure of the delay from synchronous register clock input to internal feedback of the register output signal to a combinatorial output
for which the registered output signal is used as an input. This parameter assumes no expanders are used in the logic of the combinatorial output and the
register is synchronously clocked. This parameter is tested periodically by sampling production material.
13. This specification is a measure of the delay associated with the internal register feedback path. This delay plus the register set-up time, tS, is the minimum
internal period for an internal state machine configuration. This parameter is tested periodically by sampling production material.
14. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external only feedback can operate.
15. This specification indicates the guaranteed maximum frequency at which a state machine with internal-only feedback can operate. If register output states
must also control external points, this frequency can still be observed as long as it is less than 1/tCO1. This specification assumes no expander logic is used. This
parameter is tested periodically by sampling production material.
16. This frequency indicates the maximum frequency at which the device may operate in data-path mode (dedicated input pin to output pin). This assumes that
no expander logic is used.
17. This specification indicates the guaranteed maximum frequency in synchronous mode, at which an individual output or buried register can be cycled by a
clock signal applied to either a dedicated input pin or an I/O pin.
18. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.
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