X25256

– Preliminary Information

Characteristics subject to change without notice.

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Hold (HOLD)

HOLD is used in conjunction with the CS pin to pause the

device. Once the part is selected and a serial

sequence is underway, HOLD may be used to pause the

serial communication with the controller without

resetting the serial sequence. To pause, HOLD must be

brought LOW while SCK is LOW. To resume com-

munication, HOLD is brought HIGH, again while SCK is

LOW. If the pause feature is not used, HOLD should be

held HIGH at all times.

Table 1. Instruction Set

Instruction Name

Instruction Format*

Operation

WREN

0000 0110

Set the Write Enable Latch (Enable Write Operations)

WRDI

0000 0100

Reset the Write Enable Latch (Disable Write Operations)

RDSR

0000 0101

Read Status Register

WRSR

0000 0001

Write Status Register

READ

0000 0011

Read Data from Memory Array beginning at selected address

WRITE

0000 0010

Write Data to Memory Array beginning at Selected Address (1 to 64 Bytes)

PRINCIPLES OF OPERATION

PROM designed to interface

directly with the synchronous serial peripheral interface (SPI)

of many popular microcontroller families.

The X25256 contains an 8-bit instruction register. It is

accessed via the SI input, with data being clocked in on

the rising SCK. CS must be LOW and the HOLD and

WP inputs must be HIGH during the entire operation.

Table 1 contains a list of the instructions and their

opcodes. All instructions, addresses and data are

transferred MSB first.

Data input is sampled on the first rising edge of SCK after

CS goes LOW. SCK is static, allowing the user to

stop the clock and then resume operations. If the clock

line is shared with other peripheral devices on the SPI

X25256 into a “PAUSE” condition. After releasing

HOLD, the X25256 will resume operation from the

point when HOLD was first asserted.

Write Enable Latch

The X25256 contains a “write enable” latch. This latch

must be SET before a write operation will be com-

pleted internally. The WREN instruction will set the

latch and the WRDI instruction will reset the latch. This

latch is automatically reset upon a power-up condition

and after the completion of a byte, page, or status reg-

ister write cycle.

Status Register

The RDSR instruction provides access to the status

register. The status register may be read at any time,

even during a write cycle. The status register is format- ted

as follows:

WPEN, BL0 and BL1 are set by the WRSR instruction.

WEL and WIP are read-only and automatically set by

other operations.

The Write-In-Process (WIP) bit indicates whether the

X25256 is busy with a write operation. When set to a

“1”, a write is in progress, when set to a “0”, no write is

in progress. This bit is set and reset by hardware, it

cannot be controlled by the WRSR instruction. When

reading the Status Register while an internal nonvola-

tile write is in progress, all bits output will be ‘1’. This

allows the programmer to use the WIP bit to determine

an early end of write condition. It also allows the pro-

grammer to check for “FF” or “not FF” to determine end

of write. The programmer can also use the first one or two

bits received from the Status Register (if they were

known to be zero) to determine end of write. Each of

these techniques can simplify or speed the end of non-

volatile write detection.

7

6

5

4

3

2

1

0

WPEN

X

X

BL2

BL1

BL0

WEL

WIP