5-193

FAST AND LS TTL DATA

DUAL JK NEGATIVE

EDGE-TRIGGERED FLIP-FLOP

The SN54 / 74LS114A offers common clock and common clear inputs and

individual J, K, and set inputs. These monolithic dual flip-flops are designed

so that when the clock goes HIGH, the inputs are enabled and data will be

accepted. The logic level of the J and K inputs may be allowed to change when

the clock pulse is HIGH and the bistable will perform according to the truth

table as long as minimum set-up times are observed. Input data is transferred

to the outputs on the negative-going edge of the clock pulse.

LOGIC DIAGRAM (Each Flip-Flop)

Q

5(9)

CLEAR (CD)

J

3(11)

Q

6(8)

SET (SD)

4(10)

K

2(12)

13

CLOCK (CP)

TO

OTHER

FLIPFLOP

MODE SELECT — TRUTH TABLE

OPERATING MODE

INPUTS

OUTPUTS

OPERATING MODE

SD

CD

J

K

Q

Q

Set

Reset (Clear)

*Undetermined

Toggle

Load “0” (Reset)

Load “1” (Set)

Hold

L

H

L

H

H

H

H

H

L

L

H

H

H

H

X

X

X

h

l

h

l

X

X

X

h

h

l

l

H

L

H

q

L

H

q

L

H

H

q

H

L

q

* Both outputs will be HIGH while both SD and CD are LOW, but the output states

are unpredictable if SD and CD go HIGH simultaneously.

H, h = HIGH Voltage Level

L, I = LOW Voltage Level

X = Don’t Care

l, h (q) = Lower case letters indicate the state of the referenced input (or output)

SN54/74LS114A

DUAL JK NEGATIVE

EDGE-TRIGGERED FLIP-FLOP

LOW POWER SCHOTTKY

LOGIC SYMBOL

VCC = PIN 14

GND = PIN 7

J SUFFIX

CERAMIC

CASE 632-08

N SUFFIX

PLASTIC

CASE 646-06

14

1

14

1

ORDERING INFORMATION

SN54LSXXXJ

Ceramic

SN74LSXXXN

Plastic

SN74LSXXXD

SOIC

14

1

D SUFFIX

SOIC

CASE 751A-02

4

3

13

2

1

5

6

SD

J

CP

K CD Q

Q

10

11

9

12

8

SD

J

CP

K CD Q

Q