CY7C64713/14
Document #: 38-08039 Rev. *B
Page 9 of 50
4.12.4
Endpoint Configurations
Endpoints 0 and 1 are the same for every configuration.
Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can
be either BULK or INTERRUPT. The endpoint buffers can be
configured in any 1 of the 12 configurations shown in the
vertical columns. In full-speed, BULK mode uses only the first
64 bytes of each buffer, even though memory exists for the
allocation of the isochronous transfers in BULK mode the
unused endpoint buffer space is not available for other opera-
tions. An example endpoint configuration would be:
EP2—1023 double buffered; EP6—64 quad buffered (column
8).
4.12.5
Default Alternate Settings
4.13
External FIFO Interface
4.13.1
Architecture
The FX1 slave FIFO architecture has eight 512-byte blocks in
the endpoint RAM that directly serve as FIFO memories, and
are controlled by FIFO control signals (such as IFCLK, SLCS#,
SLRD, SLWR, SLOE, PKTEND, and flags). The usable size of
these buffers depend on the USB transfer mode as described
in Section 4.12.2.
In operation, some of the eight RAM blocks fill or empty from
the SIE, while the others are connected to the I/O transfer
logic. The transfer logic takes two forms, the GPIF for internally
generated control signals, or the slave FIFO interface for
externally controlled transfers.
4.13.2
Master/Slave Control Signals
The FX1 endpoint FIFOS are implemented as eight physically
distinct 256x16 RAM blocks. The 8051/SIE can switch any of
the RAM blocks between two domains, the USB (SIE) domain
and the 8051-I/O Unit domain. This switching is done virtually
instantaneously, giving essentially zero transfer time between
“USB FIFOS” and “Slave FIFOS.” Since they are physically the
same memory, no bytes are actually transferred between
buffers.
Notes:
4.
“0” means “not implemented.”
5.
“2×” means “double buffered.”
64
64
64
64
64
1023
1023
1023
1023
1023
1023
1023
64
64
64
64
64
64
64
64
64
64
EP2
EP2
EP2
EP6
EP6
EP8
EP8
EP0 IN&OUT
EP1 IN
EP1 OUT
Figure 4-5. Endpoint Configuration
1023
1023
EP6
1023
64
64
EP8
64
64
EP6
64
64
64
64
EP2
64
64
EP4
64
64
EP2
64
64
EP4
64
64
EP2
64
64
EP4
64
64
EP2
64
64
64
64
EP2
64
64
64
64
EP2
64
64
1023
EP2
1023
1023
EP2
1023
1023
EP2
1023
64
64
EP6
1023
1023
EP6
64
64
EP8
64
64
EP6
64
64
64
64
EP6
1023
1023
EP6
64
64
EP8
64
64
EP6
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
1
2
3
4
5
6
7
8
9
10
11
12
Table 4-6. Default Alternate Settings[4, 5]
Alternate
Setting
0
1
2
3
ep0
64 64
64
64
ep1out
0 64 bulk
64 int
64 int
ep1in
0 64 bulk
64 int
64 int
ep2
0 64 bulk out (2×)64 int out (2×) 64 iso out (2×)
ep4
0 64 bulk out (2×) 64 bulk out (2×) 64 bulk out (2×)
ep6
0 64 bulk in (2×) 64 int in (2×)
64 iso in (2×)
ep8
0 64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×)