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MCF52234 Datasheet(PDF) 5 Page - Freescale Semiconductor, Inc |
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MCF52234 Datasheet(HTML) 5 Page - Freescale Semiconductor, Inc |
5 / 48 page MCF52235 Family Configurations MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0 Preliminary Freescale Semiconductor 5 1.2.1 Feature Overview • Version 2 ColdFire variable-length RISC processor core — Static operation — 32-bit address and data path on-chip — Up to 60MHz processor core frequency — Sixteen general-purpose 32-bit data and address registers — Implements ColdFire ISA_A+ with extensions to support the user stack pointer register, and 4 new instructions for improved bit processing — Enhanced Multiply-Accumulate (EMAC) unit with four 48-bit accumulators to support 32-bit signal processing algorithms — Cryptography Acceleration Unit (CAU) – Tightly-coupled coprocessor to accelerate software-based encryption and message digest functions – FIPS-140 compliant random number generator – Support for DES, 3DES, AES, MD5, and SHA-1 algorithms — Illegal instruction decode that allows for 68K emulation support • System debug support — Real time trace for determining dynamic execution path — Background debug mode (BDM) for in-circuit debugging — Real time debug support, with four user-visible hardware breakpoint registers (PC and address with optional data) that can be configured into a 1- or 2-level trigger • On-chip memories — 32 Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus masters (e.g., DMA) with standby power supply support — 256 Kbytes of interleaved Flash memory supporting 2-1-1-1 accesses • Power management — Fully static operation with processor sleep and whole chip stop modes — Very rapid response to interrupts from the low-power sleep mode (wake-up feature) — Software visible clock enable/disable for each peripheral • Fast Ethernet Controller (FEC) — 10/100 BaseT/TX capability, half duplex or full duplex — On-chip transmit and receive FIFOs — Built-in dedicated DMA controller — Memory-based flexible descriptor rings |
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