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ISL98001 Datasheet(PDF) 8 Page - Intersil Corporation |
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ISL98001 Datasheet(HTML) 8 Page - Intersil Corporation |
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8 / 31 page  8 FN6148.4 August 20, 2007 Programmable Width and Polarity Analog Video In P 1 P 2 P 3 P 4 P 5 P 6 P 7 P 8 P 0 P 9 HS OUT P 10 P 11 The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. The sampling phase setting determines its relative position to the rest of the AFE’s output signals DATACLK HSYNC IN D 0 R P/GP/BP[7:0] D 2 D 1 R S/GS/BS[7:0] t HSYNCin-to-HSout = 7.5ns + (PHASE/64 +8.5)*tPIXEL FIGURE 6. 48-BIT OUTPUT MODE, INTERLEAVED TIMING ISL98001 |
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