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C9531
Document #: 38-07034 Rev. *E
Page 4 of 10
Serial Control Registers
Byte 0: Output Register
Bit
@Pup
Name
Description
7
1
TESTEN
Test Mode Enable.
1 = Normal operation, 0 = Test mode
6
0
SSEN
Spread Spectrum modulation control bit (effective only when Bit 0 of this register is
set to a 0) 0 = OFF, 1= ON
5
1
SSSEL
SSCG Spread width select. 1 = 0.5%, 0 = 1.0% See Table 4 below for clarification
4
0
S1
S1 Bank MSB frequency control bit (effective only when Bit 0 of this register is set
to a 0)
3
0
S0
S0 Bank LSB frequency control bit (effective only when Bit 0 of this register is set
to a 0)
20
Not used
10
Not used
0
1
HWSEL
Hardware/SMBus frequency control. 1 = Hardware (pins 6, 7, and 15), 0 = SMBus
Byte 0 bits 3, 4, & 6
Table 4. Clarification Table for Byte0, bit 5
Byte0, bit6
Byte0, bit5
Description
0
0
Frequency generated from second PLL
0
1
Frequency generated from XIN
1
0
Spread @ –1.0%
1
1
Spread @ –0.5%
Table 5. Test Table
Test Function Clock
Outputs
Note
CLK
REF
Frequency
XIN/4
XIN
XIN is the frequency of the clock that is present on the
XIN input during test mode.
Byte 1: CPU Register
Bit
@Pup
Name
Description
71
Reserved
61
Reserved
5
1
REFEN
REF Output Enable
0 = Disable, 1= Enable
41
Reserved
31
Reserved
21
Reserved
11
Reserved
01
Reserved
Byte 2: PCI Register
Bit
@Pup
Name
Description
71
Reserved
61
Reserved
51
Reserved
4
1
18
CLK4 Output Enable
0 = Disable, 1= Enable