1K x 8 Registered PROM
CY7C235A
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
November 1992 – Revised March 1995
1CY 7C23 5A
Features
• CMOS for optimum speed/power
• High speed
— 18 ns address set-up
— 12 ns clock to output
• Low power
— 495 mW (commercial)
— 660 mW (military)
• Synchronous and asynchronous output enables
• On-chip edge-triggered registers
• Programmable asynchronous registers (INIT)
• EPROM technology, 100% programmable
• Slim, 300-mil, 24-pin plastic or hermetic DIP or 28-pin
LCC and PLCC
• 5V
±10% V
CC, commercial and military
• TTL-compatible I/O
• Direct replacement for bipolar PROMs
• Capable of withstanding greater than 2001V static dis-
charge
Functional Description
The CY7C235A is a high-performance 1024 word by 8 bit elec-
trically programmable read only memory packaged in a slim
300-mil plastic or hermetic DIP, 28-pin leadless chip carrier, or
28-pin plastic leaded chip carrier. The memory cells utilize
proven EPROM floating gate technology and byte-wide intelli-
gent programming algorithms.
The CY7C235A replaces bipolar devices pin for pin and offers
the advantages of lower power, superior performance, and
high programming yield. The EPROM cell requires only 12.5V
for the supervoltage, and low current requirements allow for
gang programming. The EPROM cells allow for each memory
location to be tested 100%, as each location is written into,
erased, and repeatedly exercised prior to encapsulation. Each
PROM is also tested for AC performance to guarantee that the
product will meet AC specification limits after customer pro-
gramming.
C235A-1
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
VCC
A8
A9
E
INIT
CP
O7
O6
O4
O5
O3
C235A-2
C235A-3
A8
A7
A6
A5
A4
A3
A2
A1
A0
PROGRAMMABLE
ARRAY
MULTIPLEXER
COLUMN
ADDRESS
ROW
ADDRESS
15
8-BIT
EDGE-
REGISTER
TRIGGERED
O7
O6
O5
O4
O3
O2
O1
O0
CP
CP
ES
E
ES
28
4
5
6
7
8
9
10
32 1
27
1314151617
26
25
24
23
22
21
20
11
12
19
O0
18
NC
A0
A4
A3
E
NC
INIT
ES
O7
O6
A2
A1
CP
A9
INIT
DIP
LCC/PLCC
Top View
Top View
ADDRESS
DECODER
Logic Block Diagram
Pin Configuration
Selection Guide
7C235A-18
7C235A-25
7C235A-30
7C235A-40
Minimum Address Set-Up Time (ns)
18
25
30
40
Maximum Clock to Output (ns)
12
12
15
20
Maximum Operating
Current (mA)
Commercial
90
90
90
90
Military
120
120
120